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BQ24232H_15 Datasheet, PDF (5/42 Pages) Texas Instruments – bq2423xx USB-Friendly Lithium-Ion Battery Charger and Power-Path Management IC
www.ti.com
bq24230H, bq24232H
SLUSBI8A – JANUARY 2014 – REVISED DECEMBER 2014
8.2 ESD Ratings
V(ESD) Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-
C101 (2)
VALUE
±2000
±500
UNIT
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±500 V may actually have higher performance.
8.3 Recommended Operating Conditions
VI
IIN
IOUT
IBAT
ICHG
TJ
RILIM
RISET
RTMR
RITERM
IN voltage range
IN operating voltage range
Input current, IN pin
Current, OUT pin
Current, BAT pin (discharging)
Current, BAT pin (charging)
Junction temperature
Maximum input current programming resistor
Fast-charge current programming resistor
Timer programming resistor
Termination programming resistor
'230H
'232H
'232H
MIN MAX UNIT
4.35
26 V
4.35
6.4 V
4.35 10.2
500 mA
1500 mA
1500 mA
500 mA
–40
125 °C
3.1
7.8 kΩ
1.74 34.8 kΩ
18
72 kΩ
0
15 kΩ
8.4 Thermal Information
THERMAL METRIC(1)
bq2423xx
RGT
UNIT
16 PINS
θJA
θJCtop
θJB
ψJT
ψJB
θJCbot
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
44.5
54.2
17.2
°C/W
1.0
17.1
3.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
8.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
INPUT
UVLO
Vhys(UVLO)
VIN(DT)
Vhys(INDT)
tDGL(PGOOD)
VOVP
Vhys(OVP)
PARAMETER
TEST CONDITIONS
Undervoltage lockout
Hysteresis on UVLO
Input power detection threshold
Hysteresis on VIN(DT)
Deglitch time, input power
detected status
Input overvoltage protection
threshold
Hysteresis on OVP
VIN: 0 V → 4 V
VIN: 4 V → 0 V
Input power detected when VIN > VBAT + VIN(DT)
VBAT = 3.6 V, VIN: 3.5 V → 4 V
VBAT = 3.6 V, VIN: 4 V → 3.5 V
Time measured from VIN: 0 V → 5 V 1-μs
rise time to PGOOD = LO
('230H) VIN: 5 V → 7 V
('232H) VIN: 5 V → 11 V
('230H) VIN: 7 V → 5V
('232H) VIN: 11 V → 5 V
MIN
3.2
200
55
20
6.4
10.2
TYP
MAX UNIT
3.3
3.4 V
300 mV
95
145 mV
mV
2
ms
6.6
6.8
V
10.5
10.8
110
mV
175
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