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BQ20Z655-R1_13 Datasheet, PDF (5/25 Pages) Texas Instruments – SBS 1.1-COMPLIANT GAS GAUGE AND PROTECTION ENABLED WITH IMPEDANCE TRACK™
bq20z655-R1
www.ti.com
SLUSAN9 – AUGUST 2011
TERMINAL
NO.
NAME
1
DSG
2
PACK
3
VCC
4
ZVCHG
5
GPOD
6
PMS
7
VSS
8
REG33
9
TOUT
10
VCELL+
11
ALERT
12
COM/TP
13
TS1
14
TS2
15
PRES
16
PFIN
17
SAFE
18
SMBD
19
CE
20
SMBC
21
DISP
22
VSS
23
LED1/SEG1
24
LED2/SEG2
25
LED3/SEG3
26
LED4/SEG4
27
LED5/SEG5
28
GSRP
29
GSRN
30
MRST
31
VSS
32
REG25
33
RBI
34
VSS
35
RESET
36
ASRN
37
ASRP
TERMINAL FUNCTIONS
I/O (1)
DESCRIPTION
O
IA, P
P
O
OD
I
P
P
P
—
OD
—
IA
IA
I
I
OD
I/OD
—
I/OD
I
P
I
I
I
I
I
IA
IA
I
P
P
P
P
O
IA
IA
High side N-chan discharge FET gate drive
Battery pack input voltage sense input. It also serves as device wake up when device is in shutdown
mode.
Positive device supply input. Connect to the center connection of the CHG FET and DSG FET to
ensure device supply either from battery stack or battery pack input
P-chan pre-charge FET gate drive
High voltage general purpose open drain output. Can be configured to be used in pre-charge
condition
Pre-charge mode setting input. Connect to PACK to enable 0v pre-charge using charge FET
connected at CHG pin. Connect to VSS to disable 0-V pre-charge using charge FET connected at
CHG pin.
Negative supply voltage input. Connect all VSS pins together for operation of device
3.3-V regulator output. Connect at least a 2.2-μF capacitor to REG33 and VSS
Thermistor bias supply output
Internal cell voltage multiplexer and amplifier output. Connect a 0.1-μF capacitor to VCELL+ and
VSS
Alert output. In case of short circuit condition, overload condition and watchdog time out this pin will
be triggered.
Output / open drain: LCD common connection
1st Thermistor voltage input connection to monitor temperature
2nd Thermistor voltage input connection to monitor temperature
Active low input to sense system insertion. Typically requires additional ESD protection.
Active low input to detect secondary protector status, and to allow the bq20z655-R1 to report the
status of the 2nd level protection input.
Active high output to enforce additional level of safety protection; e.g., fuse blow.
SMBus data open-drain bidirectional pin used to transfer address and data to and from the
bq20z655-R1
A logical high on this pin only affects the normal operation on the charge FET when the battery is in
charge/relax mode. For a logic low, the normal bq20z655-R1 firmware controls the charge FET.
SMBus clock open-drain bidirectional pin used to clock the data transfer to and from the
bq20z655-R1
Input: In LED mode, this is the display enable input.
Negative supply voltage input. Connect all VSS pins together for operation of device
Output / open drain: LED 1 current sink. LCD segment 1
Output / open drain: LED 2 current sink. LCD segment 2
Output / open drain: LED 3 current sink. LCD segment 3
Output / open drain: LED 4 current sink. LCD segment 4
Output / open drain: LED 5 current sink. LCD segment 5
Coulomb counter differential input. Connect to one side of the sense resistor
Coulomb counter differential input. Connect to one side of the sense resistor
Master reset input that forces the device into reset when held low. Must be held high for normal
operation. Connect to RESET for correct operation of device
Negative supply voltage input. Connect all VSS pins together for operation of device
2.5V regulator output. Connect at least a 1-mF capacitor to REG25 and VSS
RAM / Register backup input. Connect a capacitor to this pin and VSS to protect loss of
RAM/Register data in case of short circuit condition.
Negative supply voltage input. Connect all VSS pins together for operation of device
Reset output. Connect to MSRT.
Short circuit and overload detection differential input. Connect to sense resistor
Short circuit and overload detection differential input. Connect to sense resistor
(1) I = Input, IA = Analog input, I/O = Input/output, I/OD = Input/Open-drain output, O = Output, OA = Analog output, P = Power
Copyright © 2011, Texas Instruments Incorporated
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