ADS8406IPFBTG4 Datasheet, PDF (5/29 Pages) Texas Instruments – 16-BIT, 1.25 MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICRO POWER

ADS8406
www.ti.com
SLAS426A – AUGUST 2004 – REVISED DECEMBER 2004
TIMING CHARACTERISTICS
All specifications typical at –40°C to 85°C, +VA = +VBD = 5 V ^(1)(2)(3)
t_CONV
t_ACQ
t_pd1
t_pd2
t_w1
t_su1
t_w2
t_w3
t_w4
t_h1
t_d1
t_su2
t_w5
t_en
t_d2
t_d3
t_w6
t_w7
t_h2
t_su3
t_h3
t_dis
t_d5
t_su4
t_d6
t_d7
t_su(AB)
t_su5
t_h4
PARAMETER
Conversion time
Acquisition time
CONVST low to BUSY high
Propagation delay time, end of conversion to BUSY low
Pulse duration, CONVST low
Setup time, CS low to CONVST low
Pulse duration, CONVST high
CONVST falling edge jitter
Pulse duration, BUSY signal low
Pulse duration, BUSY signal high
Hold time, First data bus data transition (RD low, or CS low for
read cycle, or BYTE input changes) after CONVST low
Delay time, CS low to RD low (or BUSY low to RD low when CS =
0)
Setup time, RD high to CS high
Pulse duration, RD low time
Enable time, RD low (or CS low for read cycle) to data valid
Delay time, data hold from RD high
Delay time, BYTE rising edge or falling edge to data valid
Pulse duration, RD high
Pulse duration, CS high time
Hold time, last RD (or CS for read cycle ) rising edge to CONVST
falling edge
Setup time, BYTE transition to RD falling edge
Hold time, BYTE transition to RD falling edge
Disable time, RD high (CS high for read cycle) to 3-stated data
bus
Delay time, end of conversion to MSB data valid
Byte transition setup time, from BYTE transition to next BYTE
transition
Delay time, CS rising edge to BUSY falling edge
Delay time, BUSY falling edge to CS rising edge
Setup time, from the falling edge of CONVST (used to start the
valid conversion) to the next falling edge of CONVST (when CS =
0 and CONVST used to abort) or to the next falling edge of CS
(when CS is used to abort)
Setup time, falling edge of CONVST to read valid data (MSB) from
current conversion
Hold time, data (MSB) from previous conversion hold valid from
falling edge of CONVST
MIN
500
150
20
0
20
Min(t_ACQ)
40
0
0
50
0
2
20
20
50
0
0
50
50
50
60
MAX(t_CONV) + MAX(t_d5)
TYP
MAX UNIT
650 ns
ns
40
ns
5
ns
ns
ns
ns
10 ps
ns
610
ns
ns
ns
ns
ns
20 ns
ns
20 ns
ns
ns
ns
ns
ns
20 ns
10 ns
ns
ns
ns
500 ns
ns
MIN(t_CONV)
ns
(1) All input signals are specified with t_r = t_f = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (V_IL + V_IH)/2.
(2) See timing diagrams.
(3) All timings are measured with 20-pF equivalent loads on all data bits and BUSY pins.
5