ADS7828E Datasheet, PDF (5/22 Pages) Texas Instruments – 12-Bit, 8-Channel Sampling ANALOG-TO-DIGITAL CONVERTER with I2C Interface

TIMING DIAGRAM
SDA
t_BUF
t_LOW
t_R
t_F
SCL
t_{HD; STA}
t_{HD; STA}
STOP START
t_{HD; DAT}
t_HIGH t_{SU; DAT}
t_{SU; STA}
REPEATED
START
t_SP
t_{SU; STO}
TIMING CHARACTERISTICS⁽¹⁾
At T_A = –40°C to +85°C, +V_DD = +2.7V, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
SCL Clock Frequency
f_SCL
Bus Free Time Between a STOP and
START Condition
Hold Time (Repeated) START
Condition
LOW Period of the SCL Clock
t_BUF
t_HD;_STA
t_LOW
HIGH Period of the SCL Clock
t_HIGH
Setup Time for a Repeated START
Condition
Data Setup Time
Data Hold Time
t_SU;_STA
t_SU;_DAT
t_HD;_DAT
Rise Time of SCL Signal
t_RCL
Rise Time of SCL Signal After a
Repeated START Condition and
After an Acknowledge Bit
Fall Time of SCL Signal
t_RCL1
t_FCL
Standard Mode
Fast Mode
High-Speed Mode, C_B = 100pF max
High-Speed Mode, C_B = 400pF max
Standard Mode
Fast Mode
Standard Mode
Fast Mode
High-Speed Mode
Standard Mode
Fast Mode
High-Speed Mode, C_B = 100pF max⁽²⁾
High-Speed Mode, C_B = 400pF max⁽²⁾
Standard Mode
Fast Mode
High-Speed Mode, C_B = 100pF max⁽²⁾
High-Speed Mode, C_B = 400pF max⁽²⁾
Standard Mode
Fast Mode
High-Speed Mode
Standard Mode
Fast Mode
High-Speed Mode
Standard Mode
Fast Mode
High-Speed Mode, C_B = 100pF max⁽²⁾
High-Speed Mode, C_B = 400pF max⁽²⁾
Standard Mode
Fast Mode
High-Speed Mode, C_B = 100pF max⁽²⁾
High-Speed Mode, C_B = 400pF max⁽²⁾
Standard Mode
Fast Mode
High-Speed Mode, C_B = 100pF max⁽²⁾
High-Speed Mode, C_B = 400pF max⁽²⁾
Standard Mode
Fast Mode
High-Speed Mode, C_B = 100pF max⁽²⁾
High-Speed Mode, C_B = 400pF max⁽²⁾
4.7
1.3
4.0
600
160
4.7
1.3
160
320
4.0
600
60
120
4.7
600
160
250
100
10
0
0
0⁽³⁾
0⁽³⁾
20 + 0.1C_B
10
20
20 + 0.1C_B
10
20
20 + 0.1C_B
10
20
100
400
3.4
1.7
3.45
0.9
70
150
1000
300
40
80
1000
300
80
160
300
300
40
80
kHz
kHz
MHz
MHz
µs
µs
µs
ns
ns
µs
µs
ns
ns
µs
ns
ns
ns
µs
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES: (1) All values referred to V_IHMIN and V_ILMAX levels.
(2) For bus line loads C_B between 100pF and 400pF the timing parameters must be linearly interpolated.
(3) A device must internally provide a data hold time to bridge the undefined part between V_IH and V_IL of the falling edge of the SCLH signal. An
input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.
ADS7828
5
SBAS181C
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