LM3S8962 Datasheet, PDF (496/684 Pages) List of Unclassifed Manufacturers – Microcontroller

Ethernet Controller
4. Program the MACRCTL register to flush the receive FIFO and reject frames with bad FCS using
a value of 0x18.
5. Enable both the Transmitter and Receive by setting the LSB in both the MACTCTL and
MACRCTL registers.
6. To transmit a frame, write the frame into the TX FIFO using the Ethernet MAC Data (MACDATA)
register. Then set the NEWTX bit in the Ethernet Mac Transmission Request (MACTR) register
to initiate the transmit process. When the NEWTX bit has been cleared, the TX FIFO is available
for the next transmit frame.
7. To receive a frame, wait for the NPR field in the Ethernet MAC Number of Packets (MACNP)
register to be non-zero. Then begin reading the frame from the RX FIFO by using the MACDATA
register. To ensure that the entire packet is received, either use the DriverLib EthernetPacketGet()
API or compare the number of bytes received to the Length field from the frame to determine
when the packet has been completely read.
17.4
Ethernet Register Map
Table 17-2 on page 496 lists the Ethernet MAC registers. All addresses given are relative to the
Ethernet MAC base address of 0x4004.8000.
The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY
layer. The registers are collectively known as the MII Management registers and are detailed in
Section 22.2.4 of the IEEE 802.3 specification. Table 17-2 on page 496 also lists these MII
Management registers. All addresses given are absolute and are written directly to the REGADR field
of the Ethernet MAC Management Control (MACMCTL) register. The format of registers 0 to 15
are defined by the IEEE specification and are common to all PHY layer implementations. The only
variance allowed is for features that may or may not be supported by a specific PHY implementation.
Registers 16 to 31 are vendor-specific registers, used to support features that are specific to a
vendor's PHY implementation. Vendor-specific registers not listed are reserved.
Table 17-2. Ethernet Register Map
Offset Name
Type
Reset
Description
Ethernet MAC
0x000 MACRIS/MACIACK
0x004 MACIM
0x008 MACRCTL
0x00C MACTCTL
0x010 MACDATA
0x014 MACIA0
0x018 MACIA1
0x01C MACTHR
0x020 MACMCTL
0x024 MACMDV
0x02C MACMTXD
R/W1C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000.0000
0x0000.007F
0x0000.0008
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.003F
0x0000.0000
0x0000.0080
0x0000.0000
Ethernet MAC Raw Interrupt Status/Acknowledge
Ethernet MAC Interrupt Mask
Ethernet MAC Receive Control
Ethernet MAC Transmit Control
Ethernet MAC Data
Ethernet MAC Individual Address 0
Ethernet MAC Individual Address 1
Ethernet MAC Threshold
Ethernet MAC Management Control
Ethernet MAC Management Divider
Ethernet MAC Management Transmit Data
See
page
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496
June 22, 2010
Texas Instruments-Production Data