AFE4110 Datasheet, PDF (48/68 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

AFE4110
SLLSE48 – JANUARY 2012
ANALOG_ANACTL: Analog ana control
15
14
13
12
ana_ctl (not used)
rw-0
rw-0
rw-0
rw-0
7
6
5
4
rw-0
rw-0
rw-0
rw-0
11
rw-0
3
Reserved
rw-0
10
lpm5_en_lcd_ana_shell
rw-1
2
rw-0
rw-0
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9
8
Cp_osc_trim
rw-0
rw-0
1
0
rw-0
Reserved
Ana_ctl_cp_osc_trim
lpm5_lcd_ana_shell
ana_ctl
Bits 0-7
Bits 8-9
Bit 10
Bits 11-15
Course trimming of the 2 charge
pumps oscillator (current
trimming)
"1" powers down (~40nA) the
max_detect block inside the LCD
Block
Not used
ANALOG_PORTCTL1: Analog Analog port control 1
15
14
13
12
11
bp_dir_sync
irq_on_p3_7 irq_on_p3_6 irq_on_p3_5
rw-0
r-0
rw-0
rw-0
rw-0
7
6
5
4
3
sel_port3_7
–
r-0
r-0
rw-0
rw-0
r-0
10
irq_on_p3_4
rw-0
2
–
r-0
9
irq_on_p3_3
rw-0
8
irq_on_p3_2
rw-0
1
0
sel_port3_6
rw-0
rw-0
sel_port3_6, sel_port3_7: PORT3.6 and PORT3.7 Input multiplexer control
sel_port3_6
sel_port3_7
sel_irq_on_p3_2
sel_irq_on_p3_3
sel_irq_on_p3_4
sel_irq_on_p3_5
sel_irq_on_p3_6
sel_irq_on_p3_7
bypass_dir_sync
Bits 1,0
P3SEL1/0 = 01
P3SEL1/0 = 10
P3SEL1/0 = 11
Bits 5,4
P3SEL1/0 = 01
P3SEL1/0 = 10
P3SEL1/0 = 11
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 15
(1) force '1' when test_atpg_en_i = '1'
0,0
0,1
TA0.0
TA0.1
NEG(TA0.0)
NEG(TA0.1)
BROWNOUT ACTIVATION_SENSE
0,0
0,1
TA0.0
TA0.1
NEG(TA0.0)
NEG(TA0.1)
LCD_CP_CLK
LCD_FCLK
force '0' when test_atpg_en_i = '1'
1,0
TA0.2
NEG(TA0.2)
LFCLK
1,0
TA0.2
NEG(TA0.2)
HFCLK
1,1
TA1.1
NEG(TA1.1)
CP_1P8_COMP
1,1
LCD_COMP
NEG(LCD_COMP)
ACTIVATION_OSC_1KHZ
"1" Enable Portx.y direct DIR signal connection to TiIMERx CCx (No Dithering). "0" Enable
Portx.y DIR signal (sync to LFCLK) connection to TiIMERx CCx .Dithering enabled when
HF-CLK or EXCLK selected as Timer Clock source.⁽¹⁾
48
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