TSB81BA3EIPFP Datasheet, PDF (47/57 Pages) Texas Instruments – IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER

TSB81BA3E
www.ti.com
SLLS783A – MAY 2009 – REVISED MAY 2010
The TSB81BA3E also transfers its own self-ID packet, transmitted during the self-ID phase of bus initialization, to
the LLC. This packet it transferred to the LLC just as any other received self-ID packet.
PCLK
CTL0, CTL1
D0–D7
(a)
XX
(b)
FF (data-on)
10
(c)
(d)
SPD
d0
NOTE A: SPD = speed code, see NO TAG. d0–dn = packet data
A. SPD = speed code, see Table 35. d0-dn = packet data
Figure 24. Normal Packet Reception Timing
PCLK
00
(e)
dn
00
CTL0, CTL1
10
01
10
(a)
(b)
(c)
(d)
D0–D7
XX
FF (data-on)
STATUS
FF
SPD
d0
(data-on)
00
(e)
dn
00
NOTE A: SPD = speed code, see NO TAG. d0–dn = packet data. STATUS = status bits, see NO TAG.
A. SPD = speed code, see Table 35. d0-dn = packet data. STATUS = status bits, see Table 32.
Figure 25. Normal Packet Reception Timing With Optional Bus Status Transfer
The sequence of events for a normal packet reception is as follows:
a. Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines.
Normally, the interface is idle when receive is asserted. However, the receive operation can interrupt a status
transfer operation that is in progress so that the CTL lines can change from status to receive without an
intervening idle.
b. Data-on indication. The PHY can assert the data-on indication code on the D lines for one or more cycles
preceding the speed code. The PHY can optionally send a bus status transfer during the data-on indication
for one PCLK cycle. During this cycle, the PHY asserts status (01b) on the CTL lines while sending status
information on the D lines.
c. Speed code. The PHY indicates the speed of the received packet by asserting a speed code on the D lines
for one cycle immediately preceding packet data. The link decodes the speed code on the first receive cycle
for which the D lines are not the data-on code. If the speed code is invalid or indicates a speed higher than
that which the link is capable of handling, then the link must ignore the subsequent data.
d. Receive data. Following the data-on indication (if any) and the speed code, the PHY asserts packet data on
the D lines with receive on the CTL lines for the remainder of the receive operation.
e. Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines.
The PHY asserts at least one idle cycle following a receive operation.
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