TLV320AIC29_15 Datasheet, PDF (46/88 Pages) Texas Instruments – STEREO AUDIO CODEC WITH INTEGRATED HEADPHONE AND SPEAKER AMPLIFIERS

TLV320AIC29
SLAS494B − DECEMBER 2005 − REVISED OCTOBER 2007
www.ti.com
REGISTER 01H: Status Register
BIT
NAME
D15−D14 DAV
D13 PWRDN
D12
D11
DAVAIL
D10−D7
D6
BSTAT
D5
D4 AX1STAT
D3 AX2STAT
D2
T1STAT
D1
T2STAT
D0
RESET
VALUE
10
0
0
0
0
0
0
0
0
0
0
0
READ/
WRITE
R/W
R
R
R
R
R
R
R
R
R
R
R
FUNCTION
Data Available. These two bits program the function of the DAV pin.
00 => Reserved
01 => Acts as data available (active low) only. The DAV goes low as soon as one set of ADC
conversion(s) is completed. For scan mode, DAV remains low as long as all the
appropriate registers have not been read out.
10 => Reserved
11 => Reserved
Note:− D15−D14 should be rpogrammed to 01 for the AIC29 to operate properly.
ADC Power down status
0 => ADC is active
1 => ADC stops conversion and powers down
Reserved
Data Available Status
0 => No data available.
1 => Data is available(i.e one set of conversion is done)
Note:− This bit gets cleared only after all the converted data have been completely read out. This bit
is not valid in case of buffer mode.
Reserved
BAT Data Register Status
0 => No new data is available in BAT data register
1 => New data is available in BAT data register
Note: This bit gets cleared only after the converted data of BAT has been completely read out of the
register. This bit is not valid in case of buffer mode.
Reserved
AUX1 Data Register Status
0 => No new data is available in AUX1−data register
1 => New data is available in AUX1−data register
Note: This bit gets cleared only after the converted data of AUX1 has been completely read out of
the register. This bit is not valid in case of buffer mode.
AUX2 Data Register Status
0 => No new data is available in AUX2−data register
1 => New data is available in AUX2−data register
Note: This bit gets cleared only after the converted data of AUX2 has been completely read out of
the register. This bit is not valid in case of buffer mode.
TEMP1 Data Register Status
0 => No new data is available in TEMP1−data register
1 => New data is available in TEMP1−data register
Note: This bit gets cleared only after the converted data of TEMP1 has been completely read out of
the register. This bit is not valid in case of buffer mode.
TEMP2 Data Register Status
0 => No new data is available in TEMP2−data register
1 => New data is available in TEMP2−data register
Note: This bit gets cleared only after the converted data of TEMP2 has been completely read out of
the register. This bit is not valid in case of buffer mode.
Reserved
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