SM320F2810-EP_10 Datasheet, PDF (45/158 Pages) Texas Instruments – Digital Signal Processors

Functional Overview
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with
8 interrupts per group equals 96 possible interrupts. On the F281x and C281x, 45 of these are used by
peripherals as shown in Table 3−10.
INT1
INT2
INT11
INT12
IFR(12:1)
(Flag)
IER(12:1)
(Enable)
INTM
MUX
1
0
Global
Enable
CPU
INTx
MUX
PIEACKx
(Enable/Flag)
(Enable)
PIEIERx(8:1)
(Flag)
PIEIFRx(8:1)
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
INTx.6
INTx.7
INTx.8
From
Peripherals or
External
Interrupts
Figure 3−7. Multiplexing of Interrupts Using the PIE Block
Table 3−10. PIE Peripheral Interrupts^†
CPU
INTERRUPTS
INTx.8
INTx.7
INTx.6
PIE INTERRUPTS
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
INT1
WAKEINT
(LPM/WD)
TINT0
(TIMER 0)
ADCINT
(ADC)
XINT2
XINT1
reserved
PDPINTB
(EV-B)
PDPINTA
(EV-A)
INT2
reserved
T1OFINT
(EV-A)
T1UFINT
(EV-A)
T1CINT
(EV-A)
T1PINT
(EV-A)
CMP3INT
(EV-A)
CMP2INT
(EV-A)
CMP1INT
(EV-A)
INT3
reserved
CAPINT3
(EV-A)
CAPINT2
(EV-A)
CAPINT1
(EV-A)
T2OFINT
(EV-A)
T2UFINT
(EV-A)
T2CINT
(EV-A)
T2PINT
(EV-A)
INT4
reserved
T3OFINT
(EV-B)
T3UFINT
(EV-B)
T3CINT
(EV-B)
T3PINT
(EV-B)
CMP6INT
(EV-B)
CMP5INT
(EV-B)
CMP4INT
(EV-B)
INT5
reserved
CAPINT6
(EV-B)
CAPINT5
(EV-B)
CAPINT4
(EV-B)
T4OFINT
(EV-B)
T4UFINT
(EV-B)
T4CINT
(EV-B)
T4PINT
(EV-B)
INT6
reserved
reserved
MXINT
(McBSP)
MRINT
(McBSP)
reserved
reserved
SPITXINTA SPIRXINTA
(SPI)
(SPI)
INT7
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
INT8
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
INT9
reserved
reserved
ECAN1INT
(CAN)
ECAN0INT SCITXINTB SCIRXINTB SCITXINTA SCIRXINTA
(CAN)
(SCI-B)
(SCI-B)
(SCI-A)
(SCI-A)
INT10
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
INT11
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
INT12
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
† _{Out of the 96 possible interrupts, 45 interrupts are currently used. the remaining interrupts are reserved for future devices. However, these}
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level.
March 2004 − Revised April 2010
SGUS051B
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