TMS320VC549_07 Datasheet, PDF (43/64 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

serial port transmit timing
TMS320VC549
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS078G − SEPTEMBER 1998 − REVISED OCTOBER 2004
switching characteristics over recommended operating conditions for serial port transmit with
external clocks and frames (see Figure 22)
PARAMETER
td(DX)
th(DX)
tdis(DX)
Delay time, DX valid after CLKX rising
Hold time, DX valid after CLKX rising
Disable time, DX after CLKX rising
549-80
549-100
549-120
MIN MAX
25
−5
40
UNIT
ns
ns
ns
timing requirements over recommended operating conditions for serial port transmit with external
clocks and frames [H = 0.5t_c(CO)] (see Figure 22)
549-80
549-100
549-120
UNIT
MIN MAX
tc(SCK) Cycle time, serial port clock
6H
† _ns
th(FSX) Hold time, FSX after CLKX falling edge (see Note 1)
th(FSX)H Hold time, FSX after CLKX rising edge (see Note 1)
6
ns
2H−3‡ ns
td(FSX) Delay time, FSX after CLKX rising edge
2H−3 ns
tf(SCK) Fall time, serial port clock
6 ns
tr(SCK) Rise time, serial port clock
6 ns
tw(SCK) Pulse duration, serial port clock low/high
3H
ns
† _{The serial port design is fully static and, therefore, can operate with tc(SCK) approaching ∞. It is characterized approaching an input frequency}
of 0 Hz but tested at a much higher frequency to minimize test time.
‡ _{If the FSX pulse does not meet this specification, the first bit of serial data is driven on DX until the falling edge of FSX. After the falling edge of}
FSX, data is shifted out on DX pin. The transmit buffer-empty interrupt is generated when the th(FSX) _and th(FSX)H specification is met.
NOTE 1: Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX always are defined depending on
the source of FSX, and CLKX timings always are dependent upon the source of CLKX. Specifically, the relationship of FSX to CLKX
is independent of the source of CLKX.
CLKX
FSX
DX BIT
tc(SCK)
tw(SCK)
tf(SCK)
td(FSX)
th(FSX)H
th(FSX)
td(DX)
tw(SCK)
tr(SCK)
th(DX)
tdis(DX)
1
2
7/15
8/16
Figure 22. Serial Port Transmit Timing With External Clocks and Frames
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