LM3S6633 Datasheet, PDF (416/552 Pages) Texas Instruments – Stellaris LM3S6633 Microcontroller

Inter-Integrated Circuit (I²C) Interface
Bit/Field
0
Name
RREQ
Type
RO
Reset
0
Description
Receive Request
This bit specifies the status of the I²C slave with regards to outstanding
receive requests. If set, the I²C unit has outstanding receive data from
the I²C master and uses clock stretching to delay the master until the
data has been read from the I2CSDR register. Otherwise, no receive
data is outstanding.
Writes
I2C Slave Control/Status (I2CSCSR)
I2C Slave 0 base: 0x4002.0800
Offset 0x004
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DA
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
WO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:1
0
Name
reserved
DA
Type
RO
WO
Reset
0x00
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Device Active
Value Description
0 Disables the I²C slave operation.
1 Enables the I²C slave operation.
416
April 05, 2010
Texas Instruments-Production Data