TSB42AA9A Datasheet, PDF (41/45 Pages) Texas Instruments – StorageLynx 1394 Link-Layer Controller for ATA/ATAPI Storage Products

7 Interface Timing
7.1 ATA/ATAPI Interface Timing
StorageLynx conforms to critical and functional timing requirements for PIO modes 0–4, Multiword DMA modes 0–2,
and Ultra DMA modes 0–4, per the ATA/ATAPI–5 v3.0 specification¹. Refer to this document for details of the ATA
interface timing supported for these modes.
7.2 Serial EEPROM Interface Timing
StorageLynx conforms to the standard 2-wire serial bus timing requirements for low voltage serial EEPROMs. The
SCL signal is equivalent to a 100 kHz (maximum) clock signal.
7.3 External Flash PROM Interface
The internal 8052 can access external flash via the Flash PROM/EPROM interface. Flash read timing for this interface
is shown in Table 7–1. A timing diagram is shown in Figure 7–1.
t(per)
SCLK
ÎÎÎÎÎÎÎÎ _{ADDR (0–13)}
tsu(1)
t(fetch)
tsu(2)
ÎÎÎÎ
AD(0C–S7ÎÎ) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Valid ÎÎÎÎÎÎÎÎ
Figure 7–1. External Flash Instruction Fetch Timing
PARAMETER
t(per)
t(fetch)
tsu(1)
tsu(2)
Table 7–1. Instruction Fetch Timing Parameters
DESCRIPTION
MIN (50 MHz)
Internal 8052 clock period
20 ns
Instruction fetch time
3 SCLK cycles
Setup time from address valid until CS active
2 SCLK cycles
Data setup time to chip select
1 SCLK cycle
MIN (25 MHz)
40 ns
3 SCLK cycles
2 SCLK cycles
1 SCLK cycle
1American _{National Standards Institute, ANSI NCTIS 317-1998, AT Attachment With Packet Interface Extension—(ATA/ATAPI-5 v3.0)}
7–1