TLV2770_07 Datasheet, PDF (41/65 Pages) Texas Instruments – FAMILY OF 2.7-HIGH-SLEW-RATE RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS WITH SHUTDOWN

TLV277x, TLV277xA
FAMILY OF 2.7ĆV HIGHĆSLEWĆRATE RAILĆTOĆRAIL OUTPUT
OPERATIONAL AMPLIFIERS WITH SHUTDOWN
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
macromodel information
APPLICATION INFORMATION
Macromodel information provided was derived using Microsim Parts Release 8, the model generation
software used with Microsim PSpice . The Boyle macromodel (see Note 4) and subcircuit in Figure 64 are
generated using the TLV2772 typical electrical and operating characteristics at T_A = 25°C. Using this
information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most
cases):
D Maximum positive output voltage swing
D Unity-gain frequency
D Maximum negative output voltage swing
D Common-mode rejection ratio
D Slew rate
D Phase margin
D Quiescent power dissipation
D DC output resistance
D Input bias current
D AC output resistance
D Open-loop voltage amplification
D Short-circuit output current limit
NOTE 4: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
VDD ₊
rp
2
IN −
IN+
1
css _rss
3
iss
10
dp
j1
j2
11
12
C1
+
vc
r2
−
53
dc
egnd
9
+
vb
−
99
+
− ^fb
C2
6
gcm
ga
dln
ro2 ⁹⁰
hlim
+ _dlp
−
7
+
vlim
−
8
91
+
vlp
−
92
−
vln
+
GND
rd1
4
rd2
54 ^de
−+
ve
* TLV2772 operational amplifier macromodel subcircuit
* created using Parts release 8.0 on 12/12/97 at 10:08
* Parts is a MicroSim product.
*
* connections: noninverting input
*
| inverting input
*
| | positive power supply
*
| | | negative power supply
*
| | | | output
*
|| | ||
.subckt TLV2772
12345
*
c1
11 12 2.8868E-12
c2
6 7 10.000E−12
css
10 99 2.6302E−12
dc
5 53 dy
de
54 5 dy
dlp
90 91 dx
dln
92 90 dx
dp
4 3 dx
egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5
fb
7 99 poly(5) vb vc ve vlp vln 0
15.513E6 −1E3 1E3 16E6 −16E6
ga
6 0 11 12 188.50E−6
gcm
0
6
10 99 9.4472E−9
*$
ro1
5
iss
3
hlim
90
j1
11
j2
12
r2
6
rd1
4
rd2
4
ro1
8
ro2
7
rp
3
rss
10
vb
9
vc
3
ve
54
vlim
7
vlp
91
vln
0
.model dx
.model dy
.model jx1
.model jx2
.ends
OUT
10 dc 145.50E−6
0 vlim 1K
2 10 jx1
1 10 jx2
9 100.00E3
11 5.3052E3
12 5.3052E3
5 17.140
99 17.140
4 4.5455E3
99 1.3746E6
0 dc 0
53 dc .82001
4 dc .82001
8 dc 0
0 dc 47
92 dc 47
D(Is=800.00E−18)
D(Is=800.00E−18 Rs=1m Cjo=10p)
PJF(Is=2.2500E−12 Beta=244.20E−6
+ Vto=−.99765)
PJF(Is=1.7500E−12 Beta=244.20E−6
+ Vto=−1.002350)
Figure 64. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
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