ADSP-21060LCW-160 Datasheet, PDF (41/64 Pages) Analog Devices – SHARC Processor

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Table 27. Link Ports—Transmit
5V
3.3 V
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
t_SLACH
LACK Setup Before LCLK High
19
19
ns
t_HLACH
LACK Hold After LCLK High
–6.75
–6.5
ns
Switching Characteristics
t_DLCLK
t_DLDCH
t_HLDCH
t_LCLKTWL
t_LCLKTWH
t_DLACLK
Data Delay After CLKIN
Data Delay After LCLK High¹
Data Hold After LCLK High²
LCLK Width Low³
LCLK Width High⁴
LCLK Low Delay After LACK High
–2.0
(t_CK/4) – 1
(t_CK/4) – 1.25
(t_CK/4) + 9
8
2.25
(t_CK/4) + 1.25
(t_CK/4) + 1
(3  t_CK/4) + 16.5
–2
(t_CK/4) – 0.75
(t_CK/4) – 1.5
(t_CK/4) + 9
8
ns
2.25
ns
ns
(t_CK/4) + 1.5
ns
(t_CK/4) + 1
ns
(3  t_CK/4) + 16.5 ns
1 _{For ADSP-21060/ADSP-21060C, specification is 2.5 ns max.}
2 _{For ADSP-21062L, specification is –2.25 ns min.}
3 _{For ADSP-21060, specification is (tCK/4) – 1 ns min, (tCK/4) + 1 ns max; for ADSP-21060C/ADSP-21062L, specification is (tCK/4) – 1 ns min, (tCK/4) + 1.5 ns max.}
4 _{For ADSP-21060, specification is (tCK/4) – 1 ns min, (tCK/4) + 1 ns max; for ADSP-21060C, specification is (tCK/4) – 1.5 ns min, (tCK/4) + 1 ns max.}
Rev. H | Page 41 of 64 | March 2013