VSP2265 Datasheet, PDF (40/88 Pages) Texas Instruments – CCD Signal Processor with Timing Generator for Digital Cameras

Serial Interface Timing Specification
3.1.17 SHP Register
SD15 SD14 SD13 SD12 SD11 SD10
0
1
0
0
1
0
default
SD9
SHP
ext
0
SD8 SD7 SD6 SD5 SD4 SD3
SD2
SD1
SD0
SHP 0
0
0
0 SHPfa3 SHPfa2 SHPfa1 SHPfa0
mon
MSB
LSB
1
0
0
0
0
1
0
0
0
BIT
SD9
SD8
SD3–SD0
NAME
SHP ext
SHP mon
SHPfa[3:0]
DEFAULT VALUE
0
1
1000
DESCRIPTION
External selection:
0 = Without use of external SHP clock
1 = Use external SHP clock
Monitor selection:
0 = SHP clock monitor
1 = SHP clock without monitor
SHP delay edge definition using 4 bits
1111 = SHP delay maximum
:
1000 = SHP delay typical
:
0000 = SHP delay minimum
3.1.18 SHD Register
SD15 SD14 SD13 SD12 SD11 SD10 SD9 SD8 SD7 SD6 SD5 SD4 SD3
SD2
SD1
SD0
0
1
0
1
0
0 SHD SHD 0
0
0
0 SHDfa3 SHDfa2 SHDfa1 SHDfa0
ext mon
MSB
LSB
default
0
1
0
0
0
0
1
0
0
0
BIT
SD9
SD8
SD3–SD0
NAME
SHD ext
SHD mon
SHDfa[3:0]
DEFAULT VALUE
0
1
1000
DESCRIPTION
External selection:
0 = Without use of external SHD clock
1 = Use external SHD clock
Monitor selection:
0 = SHD clock monitor
1 = SHD clock without monitor
SHD delay edge definition using 4 bits
1111 = SHD delay maximum
:
1000 = SHD delay typical
:
0000 = SHD delay minimum
SLES056—December 2002
VSP2265
37