TAS5706A Datasheet, PDF (40/63 Pages) Texas Instruments – 20-W Stereo Digital Audio Power Amplifier with EQ and DRC

TAS5706A
SLOS606 – AUGUST 2008 ................................................................................................................................................................................................ www.ti.com
10. This completes the initialization sequence. From this step on, no further constraints are imposed on PDN,
MUTE, and clocks.
11. During normal operation the user may do the following:
a. Write to the master or individual-channel volume registers.
b. Write to the soft-mute register.
c. Write to the clock and serial data interface format registers (in manual clock mode only).
d. Write to bit 6 of register 0x05 to enter/exit all-channel shutdown. No other bits of register 0x05 may be
altered. After issuing the all-channel shutdown command, no further I²C transactions that address this
device are allowed for a period of at least: 1 ms + 1.3 × (period specified in start/stop register 0x1A) .
e. PDN may be asserted (low) at any time. Once PDN is asserted, no I²C transactions that address this
device may be issued until PDN has been deasserted and the part has returned to active mode.
NOTE: When the device is in a powered down state (initiated via PDN), the part is not reset if RESET
is asserted.
NOTE: Once RESET is asserted, and as long as the part is in a reset state, the part does not power
down if PDN is asserted. For powering the part down, a negative edge on PDN must be issued when
RESET is high and the part is not in a reset state.
NOTE: No registers besides those explicitly listed in Steps a.–d. should be altered during normal
operation (i.e., after exiting all-channel shutdown).
NOTE: No registers should be read during normal operation (i.e., after exiting all-channel shutdown) .
12. To reconfigure registers:
a. Return to all-channel shutdown (observe the shutdown wait time as specified in Step 11.d.).
b. Drive PDN = 1, and hold MUTE stable.
c. Provide a stable MCLK, LRCLK, and SCLK.
d. Repeat configuration starting from step (6).
Table 2. Serial Control Interface Register Summary ⁽¹⁾
SUBADDRESS
REGISTER NAME
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
Clock control register
Device ID register
Error status register
System control register 1
Serial data interface
register
System control register 2
Soft mute register
Master volume
Channel 1 vol
Channel 2 vol
Channel 3 vol
Channel 4 vol
HP volume
Channel 6 vol
Volume configuration
register
Modulation limit register
IC delay channel 1
NO. OF
BYTES
1
1
1
1
1
CONTENTS
A u indicates unused bits.
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
1
Description shown in subsequent section
1
Description shown in subsequent section
1
Description shown in subsequent section
1
Description shown in subsequent section
1
Description shown in subsequent section
1
Description shown in subsequent section
1
Description shown in subsequent section
1
Description shown in subsequent section
1
Description shown in subsequent section
1
Description shown in subsequent section
1
Reserved ⁽²⁾
1
Description shown in subsequent section
1
Description shown in subsequent section
INITIALIZATION
VALUE
0x6C
0x28
0x00
0xA0
0x05
0x40
0x00
0xFF (mute)
0x30 (0 dB)
0x30 (0 dB)
0x30 (0 dB)
0x30 (0 dB)
0x30 (0 dB)
0x30 (0 dB)
0x91
0x02
0x4C
(1) Biquad definition is given in Figure 47.
(2) Reserved registers should not be accessed.
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