TPS54362-Q1_15 Datasheet, PDF (4/40 Pages) Texas Instruments – TPS54362-Q1 3-A, 60-V Step-Down DC-DC Converter With Low I(q)

TPS54362-Q1
SLVS845G – MARCH 2009 – REVISED AUGUST 2014
5 Pin Configuration and Functions
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PIN
NAME
NO.
BOOT
20
Cdly
9
COMP
15
EN
5
GND
10
LPM
4
NU
1
2
OV_TH
12
PH
17
Rslew
7
RST
8
RST_TH
13
RT
6
SS
11
SYNC
3
VIN
18
19
VReg
16
VSENSE
14
Thermal pad
PWP 20-Pin Package
20-Pin HTSSOP With Thermal Pad
Top View
NU
1
NU
2
SYNC
3
LPM
4
EN
5
RT
6
Rslew
7
RST
8
Cdly
9
GND
10
20
BOOT
19
VIN
18
VIN
17
PH
16
VReg
15
COMP
14
VSENSE
13
RST_TH
12
OV_TH
11
SS
NU – Make no external connection
Pin Functions
I/O
DESCRIPTION
O External bootstrap capacitor to PH to drive the gate of the internal switching FET
I/O External capacitor to ground to program power-on-reset delay.
I/O Error-amplifier output to connect external compensation components
I Enable pin, internally pulled up. This pin requires an external pullup or pulldown to enable or disable the
device.
O Ground pin
I Low-power mode control using digital input signal. An internal pulldown resistor of 62 kΩ (typical)
connects to ground.
— Connect to ground
I Sense input for overvoltage detection on regulated output. This pin monitors the V_(Vreg) output voltage as
divided by the external resistor network connecting between the VReg pin and ground. The resistor
network programs the threshold voltage.
O Source of the internal switching FET
O External resistor to ground to control the slew rate of the internal switching FET
O Active-low, open-drain reset output connected to external bias voltage through a resistor, asserted high
after the device starts regulating
I Sense input for undervoltage and reset voltage detection on regulated output to initiate a reset-output
signal. This pin monitors the V_(Vreg) output voltage as divided by the external resistor network connecting
between the VReg pin and ground. The resistor network programs the threshold voltage.
O External resistor to ground to program the internal oscillator frequency
I/O External capacitor to ground to program soft-start time
I External synchronization clock input to override the internal oscillator clock. An internal pulldown resistor
of 62 kΩ (typical) connects to ground.
I Unregulated input voltage. Connect pin 18 and pin 19 together externally.
I Internal low-side FET to load output during start-up or limit overshoot
I Inverting node of error amplifier for voltage-mode control
— The thermal pad connects electrically to exposed ground pad on PCB for proper thermal performance.
4
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