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TLC7628C Datasheet, PDF (4/10 Pages) Texas Instruments – DUAL 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS | |||
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TLC7628C, TLC7628E, TLC7628I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS063A â APRIL 1989 â REVISED MAY 1995
operating characteristics over recommended ranges of operating free-air temperature and VDD,
VrefA = VrefB = 10 V, VOA and VOB at 0 V (unless otherwise noted)
PARAMETER
Linearity error
Settling time (to 1/2 LSB)
See Note 1
Gain error
See Note 2
AC feedthrough
REFA to OUTA
REFB to OUTB
Temperature coefficient of gain
Propagation delay (from digital input to
90% of final analog output current)
See Note 3
See Note 4
TEST CONDITIONS
Full range
25°C
Full range
25°C
MIN TYP MAX
UNIT
± 1/2
LSB
100
ns
±3
LSB
±2
â 65
dB
â 75
± 0.0035 %FSR/°C
80
ns
Channel-to-channel REFA to OUTB
isolation
REFB to OUTA
See Note 5
See Note 6
25°C
25°C
80
dB
80
Digital-to-analog glitch impulse area
Measured for code transition from 00000000 to 11111111,
TA = 25°C
330
nVâ¢s
Digital crosstalk
Measured for code transition from 00000000 to 11111111,
TA = 25°C
60
nVâ¢s
Harmonic distortion
Vi = 6 V, f = 1 kHz, TA = 25°C
â 85
dB
NOTES: 1. OUTA, OUTB load = 100 â¦, Cext = 13 pF; WR and CS at 0 V; DB0âDB7 at 0 V to VDD or VDD to 0 V.
2. Gain error is measured using an internal feedback resistor. Nominal full scale range (FSR) = Vref â 1 LSB. Both DAC latches are
loaded with 11111111.
3. Vref = 20 V peak-to-peak, 10-kHz sine wave
4. VrefA = VrefB = 10 V; OUTA/OUTB load = 100 â¦, Cext = 13 pF; WR and CS at 0 V; DB0âDB7 at 0 V to VDD or VDD to 0 V.
5. VrefA = 20 V peak-to-peak, 10-kHz sine wave; VrefB = 0
6. VrefB = 20 V peak-to-peak, 10-kHz sine wave; VrefA = 0
CS
DACA/DACB
WR
DB0 â DB7
ÃÃÃ tsu(CS)
th(CS)
1.3 V
3.5 V
1.3 V
ÃÃÃÃ tsu(DAC)
0.3 V
th(DAC)
3.5 V
1.3 V
ÃÃÃÃÃÃ tw(WR)
1.3 V
0.3 V
3.5 V
1.3 V
ÃÃÃÃÃÃ 1.3 V
tsu(D)
th(D)
0.3 V
3.5 V
1.3 V
Data In Stable
1.3 V
0.3 V
For all input signals, tr = tf = 5 ns (10% to 90% points).
Figure 1. Setup and Hold Times
4
⢠POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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