SN74AS4374B Datasheet, PDF (4/5 Pages) Texas Instruments – OCTAL EDGE-TRIGGERED D-TYPE DUAL-RANK FLIP-FLOP WITH 3-STATE OUTPUTS

SN74AS4374B
OCTAL EDGE-TRIGGERED D-TYPE DUAL-RANK FLIP-FLOP
WITH 3-STATE OUTPUTS
SDAS109D – APRIL 1989 – REVISED JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
7V
From Output
Under Test
CL = 50 pF
(see Note A)
Open
S1
R1 = 500 Ω
Test Point
R2 = 500 Ω
SWITCH POSITION TABLE
TEST
S1
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Open
Open
Open
Closed
Open
Closed
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
Timing
Input
tsu
Data
Input
1.3 V
th
1.3 V
1.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3.5 V
0.3 V
3.5 V
0.3 V
Input
tPLH
In-Phase
Output
tPHL
Out-of-Phase
Output
1.3 V
1.3 V
1.3 V
1.3 V
3.5 V
0.3 V
tPHL
VOH
1.3 V
VOL
tPLH
VOH
1.3 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
High-Level
Pulse
Low-Level
Pulse
1.3 V
tw
1.3 V
1.3 V
1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
Output
Control
tPZL
Waveform 1
S1 Closed
(see Note B)
tPZH
Waveform 2
S1 Open
(see Note B)
1.3 V
1.3 V
tPHZ
1.3 V
1.3 V
tPLZ
0.3 V
3.5 V
VOL
0.3 V
VOH
0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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