LP3965EMP-ADJ Datasheet, PDF (4/36 Pages) Texas Instruments – LP3962/LP3965 1.5A Fast Ultra Low Dropout Linear Regulators

LP3962, LP3965
SNVS066H – MAY 2000 – REVISED APRIL 2013
Pin #
1
2
3
4
Name
SD
V_IN
V_OUT
ERROR
Pin Descriptions for SOT-223-5 Package
LP3962
Function
Name
Shutdown
SD
Input Supply
Output Voltage
ERROR Flag
V_IN
V_OUT
SENSE/ADJ
5
GND
Ground
GND
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LP3965
Function
Shutdown
Input Supply
Output Voltage
Remote Sense Pin or Output
Adjust Pin
Ground
Pin #
1
2
3
4
5
Pin Descriptions for TO-220-5 and SFM/TO-263-5 Packages
LP3962
LP3965
Name
Function
Name
Function
SD
Shutdown
SD
Shutdown
V_IN
GND
Input Supply
Ground
V_IN
GND
Input Supply
Ground
V_OUT
ERROR
Output Voltage
ERROR Flag
V_OUT
SENSE/ADJ
Output Voltage
Remote Sense Pin or Output
Adjust Pin
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings ⁽¹⁾⁽²⁾
Storage Temperature Range
Lead Temperature (Soldering, 5 sec.)
ESD Rating ⁽³⁾
Power Dissipation ⁽⁴⁾
Input Supply Voltage (Survival)
Shutdown Input Voltage (Survival)
Output Voltage (Survival), ⁽⁵⁾, ⁽⁶⁾
I_OUT (Survival)
Maximum Voltage for ERROR Pin
Maximum Voltage for SENSE Pin
−65°C to +150°C
260°C
2 kV
Internally Limited
−0.3V to +7.5V
−0.3V to V_IN+0.3V
−0.3V to +7.5V
Short Circuit Protected
V_IN+0.3V
V_OUT+0.3V
(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which
the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and test conditions,
see Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.
(4) At elevated temperatures, devices must be derated based on package thermal resistance. The devices in TO-220 package must be
derated at θ_jA = 50°C/W (with 0.5in², 1oz. copper area), junction-to-ambient (with no heat sink). The devices in the SFM/TO-263
surface-mount package must be derated at θ_jA = 60°C/W (with 0.5in², 1oz. copper area), junction-to-ambient. The devices in SOT-223
package must be derated at θ_jA = 90°C/W (with 0.5in², 1oz. copper area), junction-to-ambient.
(5) If used in a dual-supply system where the regulator load is returned to a negative supply, the LP396X output must be diode-clamped to
ground.
(6) The output PMOS structure contains a diode between the V_IN and V_OUT terminals. This diode is normally reverse biased. This diode will
get forward biased if the voltage at the output terminal is forced to be higher than the voltage at the input terminal. This diode can
typically withstand 200mA of DC current and 1Amp of peak current.
4
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