LM5045_15 Datasheet, PDF (4/46 Pages) Texas Instruments – Full-Bridge PWM Controller With Integrated MOSFET Drivers

LM5045
SNVS699H – FEBRUARY 2011 – REVISED JANUARY 2015
www.ti.com
NAME
AGND
BST1
BST2
PIN
HTSSOP
9
25
WQFN
5
21
18
14
COMP
6
2
CS
HO1
HO2
HS1
HS2
LO1
LO2
4
28
26
22
17
13
27
23
16
12
23
19
20
16
OVP/OTP
2
26
PGND
RAMP
22
18
3
27
RD1
RD2
REF
10
6
11
7
7
3
RES
12
8
RT/SYNC
8
4
SLOPE
5
1
Pin Functions
I/O
DESCRIPTION
APPLICATION INFORMATION
O
Analog Ground
Connect directly to the Power Ground.
Bootstrap capacitors connected between BST1, 2 and SW1,
I
Gate Drive Bootstrap
2 provide bias supply for the high side HO1, 2 gate drivers.
External diodes are required between VCC and BST1, 2 to
charge the bootstrap capacitors when SW1, 2 are low.
An external opto-coupler connected to the COMP pin
sources current into an internal NPN current mirror. The
I
Input to the Pulse Width PWM duty cycle is at maximum with zero input current, while
Modulator
1 mA reduces the duty cycle to zero. The current mirror
improves the frequency response by reducing the AC voltage
across the opto-coupler.
I
Current Sense Input
If CS exceeds 750 mV the PWM output pulse will be
terminated, entering cycle-by-cycle current limit. An internal
switch holds CS low for 40 nS after either output switches
high to blank leading edge transients.
High side PWM outputs capable of driving the upper
O
High Side Output Driver MOSFET of the bridge with 1.5-A peak source and 2-A peak
sink current.
I
Switch Node
Common connection of the high side FET source, low side
FET drain and transformer primary winding.
O
Low Side Output Driver
Alternating output of the PWM gate driver. Capable of 1.5-A
peak source and 2-A peak sink current.
An external voltage divider from the input power supply sets
the shutdown level during an over-voltage condition.
I
Overvoltage Protection
Alternatively, an external NTC thermistor voltage divider can
be used to set the shutdown temperature. The threshold is
1.25 V. Hysteresis is set by an internal current that sources
20 µA of current into the external resistor divider.
O
Power Ground
Connect directly to Analog Ground
Modulation ramp for the PWM comparator. This ramp can be
I
Input to PWM Comparator
a signal representative of the primary current (current mode)
or proportional to the input voltage (feed-forward voltage
mode). This pin is reset to GND at the end of every cycle.
I
Synchronous Rectifier
Leading Edge Delay
The resistance connected between RD1 and AGND sets the
delay from the falling edge of SR1 or SR2 and the rising
edge of HO2/LO1 or HO1/LO2, respectively.
I
Synchronous Rectifier
Trailing Edge Delay
The resistance connected between RD2 and AGND sets the
delay from the falling edge of HO1/LO2 or HO2/LO1 and the
rising edge of SR2 or SR1, respectively.
O
Output of a 5V reference
Maximum output current is 15 mA. Locally decouple with a
0.1-µF capacitor.
I
Restart Timer
Whenever the CS pin exceeds the 750-mV cycle-cycle
current limit threshold, 30-µA current is sourced into the RES
capacitor for the remainder of the PWM cycle. If the RES
capacitor voltage reaches 1.0 V, the SS capacitor is
discharged to disable the HO1, HO2, LO1, LO2 and SR1,
SR2 outputs. The SS pin is held low until the voltage on the
RES capacitor has been ramped between 2-V and 4-V eight
times by 10-µA charge and 5-µA discharge currents. After
the delay sequence, the SS capacitor is released to initiate a
normal start-up sequence.
O
Oscillator Frequency
Control and Frequency
Synchronization
The resistance connected between RT and AGND sets the
oscillator frequency. Synchronization is achieved by AC
coupling a pulse to the RT/SYNC pin that raises the voltage
at least 1.5 V above the 2-V nominal bias level.
O
Slope Compensation
Current
A ramping current source from 0 to 100 µA is provided for
slope compensation in current mode control. This pin can be
connected through an appropriate resistor to the CS pin to
provide slope compensation. If slope compensation is not
required, SLOPE must be tied to ground.
4
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