DS90C031BTMX Datasheet, PDF (4/19 Pages) Texas Instruments – DS90C031B LVDS Quad CMOS Differential Line Driver

DS90C031B
SNLS051B – MARCH 1999 – REVISED MARCH 2013
www.ti.com
Switching Characteristics
V_CC = +5.0V, T_A = +25°C ^{(1) (2) (3)}
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t_PHLD
t_PLHD
t_SKD
t_SK1
t_TLH
t_THL
t_PHZ
t_PLZ
t_PZH
t_PZL
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
Differential Skew |t_PHLD – t_PLHD|
Channel-to-Channel Skew ⁽⁴⁾
Rise Time
Fall Time
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
R_L = 100Ω, C_L = 5 pF
(Figure 3 and Figure 4)
R_L = 100Ω, C_L = 5 pF
(Figure 5 and Figure 6)
1.0
2.0
3.0
ns
1.0
2.1
3.0
ns
0
80
400
ps
0
300
600
ps
0.35
1.5
ns
0.35
1.5
ns
2.5
10
ns
2.5
10
ns
2.5
10
ns
2.5
10
ns
(1) All typicals are given for: V_CC = +5.0V, T_A = +25°C.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z_O = 50Ω, t_r ≤ 6 ns, and t_f ≤ 6 ns.
(3) C_L includes probe and jig capacitance.
(4) Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in the
same chip with an event on the inputs.
Switching Characteristics
V_CC = +5.0V ± 10%, T_A = −40°C to +85°C ^{(1) (2) (3)}
Symbol
Parameter
t_PHLD
t_PLHD
t_SKD
t_SK1
t_SK2
t_TLH
t_THL
t_PHZ
t_PLZ
t_PZH
t_PZL
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
Differential Skew |t_PHLD – t_PLHD|
Channel-to-Channel Skew ⁽⁴⁾
Chip to Chip Skew ⁽⁵⁾
Rise Time
Fall Time
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
Conditions
R_L = 100Ω, C_L = 5 pF
(Figure 3 and Figure 4)
R_L = 100Ω, C_L = 5 pF
(Figure 5 and Figure 6)
Min
Typ
Max
0.5
2.0
3.5
0.5
2.1
3.5
0
80
900
0
0.3
1.0
3.0
0.35
2.0
0.35
2.0
2.5
15
2.5
15
2.5
15
2.5
15
Units
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
(1) All typicals are given for: V_CC = +5.0V, T_A = +25°C.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z_O = 50Ω, t_r ≤ 6 ns, and t_f ≤ 6 ns.
(3) C_L includes probe and jig capacitance.
(4) Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in the
same chip with an event on the inputs.
(5) Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
4
Submit Documentation Feedback
Product Folder Links: DS90C031B
Copyright © 1999–2013, Texas Instruments Incorporated