DRV8823_15 Datasheet, PDF (4/21 Pages) Texas Instruments – 4-BRIDGE SERIAL INTERFACE MOTOR DRIVER

DRV8823
SLVS913D – JANUARY 2009 – REVISED JANUARY 2010
VM 1
VM 2
AOUT2 3
AISEN 4
AOUT1 5
NC 6
CP1 7
CP2 8
VCP 9
PGND ¹⁰
Solder these
pins to copper
heatsink area
PGND 11
PGND 12
PGND 13
PGND 14
PGND 15
V3P3 16
ABVREF 17
CDVREF 18
TEST 19
DOUT2 ²⁰
DISEN ²¹
DOUT1 22
VM 23
VM ²⁴
DCA PACKAGE
48 BOUT1
47 BISEN
46 BOUT2
45 SCS
44 NC
43 RESETn
42 SLEEPn
41 NC
40 NC
39 PGND
38 PGND
37 PGND
36 PGND
35 PGND
Solder these
pins to copper
heatsink area
34 PGND
33 SCLK
32 _TEST
31 SDATA
30 _SSTB
29 _TEST
28 TEST
27 _COUT1
26 CISEN
25 _COUT2
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ABSOLUTE MAXIMUM RATINGS^{(1) (2)}
over operating free-air temperature range (unless otherwise noted)
V_M
V_I
I_O(peak)
I_O
P_D
T_J
T_A
T_stg
Power supply voltage range
Logic input voltage range⁽³⁾
Peak motor drive output current, t < 1 ms
Motor drive output current⁽⁴⁾
Continuous total power dissipation
Operating virtual junction temperature range
Operating ambient temperature range
Storage temperature range
–0.3 to 34
V
–0.5 to 5.75
V
Internally limited
1.5
A
See Dissipation Ratings Table
–40 to 150
°C
–40 to 85
°C
–60 to 150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) Input pins may be driven in this voltage range regardless of presence or absence of V_M.
(4) Power dissipation and thermal limits must be observed.
DISSIPATION RATINGS
BOARD
Low-K ⁽¹⁾
Low-K ⁽²⁾
High-K ⁽³⁾
High-K ⁽⁴⁾
PACKAGE
DCA
R_qJA
75.7°C/W
32°C/W
30.3°C/W
22.3°C/W
DERATING FACTOR
ABOVE T_A = 25°C
13.2 mW/°C
31.3 mW/°C
33 mW/°C
44.8 mW/°C
T_A < 25°C
1.65 W
3.91 W
4.13 W
5.61 W
T_A = 70°C
1.06 W
2.50 W
2.48 W
3.59 W
T_A = 85°C
0.86 W
2.03 W
2.15 W
2.91 W
(1) The JEDEC Low-K board used to derive this data was a 76-mm x 114-mm, 2-layer, 1.6-mm thick PCB with no backside copper.
(2) The JEDEC Low-K board used to derive this data was a 76-mm x 114-mm, 2-layer, 1.6-mm thick PCB with 25-cm² 2-oz copper on back
side.
(3) The JEDEC High-K board used to derive this data was a 76-mm x 114-mm, 4-layer, 1.6-mm thick PCB with no backside copper and
solid 1-oz internal ground plane.
(4) The JEDEC High-K board used to derive this data was a 76-mm x 114-mm, 4-layer, 1.6-mm thick PCB with 25-cm² 1-oz copper on back
side and solid 1-oz internal ground plane.
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