DRV8818 Datasheet, PDF (4/20 Pages) Texas Instruments – STEPPER MOTOR CONTROLLER IC

DRV8818
SLVSAX9A – SEPTEMBER 2011 – REVISED FEBRUARY 2012
www.ti.com
PWP (HTSSOP) PACKAGE
ISENA 1
HOME 2
DIR 3
AOUT1 4
DECAY 5
RCA 6
GND 7
VREF 8
RCB 9
VCC 10
BOUT1 11
USM1 12
USM0 13
ISENB 14
GND
(PPAD)
28 VMA
27 SLEEPn
26 ENABLEn
25 AOUT2
24 CP2
23 CP1
22 VCP
21 GND
20 VGD
19 STEP
18 BOUT2
17 RESETn
16 SRn
15 VMB
ABSOLUTE MAXIMUM RATINGS^{(1) (2) (3)}
MIN
MAX UNIT
V_MX
Power supply voltage range
V_CC
Power supply voltage range
Digital pin voltage range
–0.3
35 V
–0.3
7V
–0.5
7V
V_REF
Input voltage range
ISENSEx pin voltage range
–0.3 V
–0.3
V_CC V
0.5 V
I_O(peak)
P_D
T_J
T_stg
Peak motor drive output current
Continuous total power dissipation
Operating junction temperature range
Storage temperature range
Internally limited
See Thermal Information table
–40
150 °C
–60
150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) Power dissipation and thermal limits must be observed.
THERMAL INFORMATION
THERMAL METRIC⁽¹⁾
DRV8818
PWP
UNITS
θ_JA
θ_JCtop
θ_JB
ψ_JT
ψ_JB
θ_JCbot
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case (top) thermal resistance⁽³⁾
Junction-to-board thermal resistance⁽⁴⁾
Junction-to-top characterization parameter⁽⁵⁾
Junction-to-board characterization parameter⁽⁶⁾
Junction-to-case (bottom) thermal resistance⁽⁷⁾
28 PINS
32.2
16.3
14
0.5
13.8
2.1
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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