DRV8811 Datasheet, PDF (4/19 Pages) Texas Instruments – STEPPER MOTOR CONTROLLER IC

DRV8811
SLVS865D – SEPTEMBER 2008 – REVISED JULY 2009 ................................................................................................................................................. www.ti.com
PWP (HTSSOP) PACKAGE
ISENA 1
HOME 2
DIR 3
AOUT1 4
DECAY 5
RCA 6
GND 7
VREF 8
RCB 9
VCC 10
BOUT1 11
USM1 12
USM0 13
ISENB 14
GND
(PPAD)
28 VMA
27 SLEEPn
26 ENABLEn
25 AOUT2
24 CP2
23 CP1
22 VCP
21 GND
20 VGD
19 STEP
18 BOUT2
17 RESETn
16 SRn
15 VMB
ABSOLUTE MAXIMUM RATINGS^(1)(2)(3)
over operating free-air temperature range (unless otherwise noted)
V_MX
V_CC
V_REF
I_O(peak)
I_O
P_D
T_J
T_A
T_stg
Power supply voltage range
Power supply voltage range
Digital pin voltage range
Input voltage range
ISENSEx pin voltage range
Peak motor drive output current, t < 1 µs
Continuous motor drive output current
Continuous total power dissipation
Operating virtual junction temperature range
Operating ambient temperature range
Storage temperature range
MIN
MAX UNIT
–0.3
40 V
–0.3
7V
–0.5
–0.3 V
–0.3
V_CC V
V_CC V
0.5 V
6A
±2.5 A
See Dissipation Ratings Table
0
150 °C
–40
85 °C
–60
150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) Power dissipation and thermal limits must be observed.
DISSIPATION RATINGS
BOARD
Low-K ⁽¹⁾
Low-K ⁽²⁾
High-K ⁽³⁾
High-K ⁽⁴⁾
PACKAGE
PWP
PWP
PWP
PWP
R_θJA
67.5 °C/W
39.5 °C/W
33.5 °C/W
28 °C/W
DERATING
FACTOR
ABOVE T_A = 25°C
14.8 mW/°C
25.3 mW/°C
29.8 mW/°C
35.7 mW/°C
T_A < 25°C
1.85 W
3.16 W
3.73 W
4.46 W
T_A = 70°C
1.18 W
2.02 W
2.38 W
2.85 W
T_A = 85°C
0.96 W
1.64 W
1.94 W
2.32 W
(1) The JEDEC Low-K board used to derive this data was a 76 mm x 114 mm, 2-layer, 1.6 mm thick PCB with no backside copper.
(2) The JEDEC Low-K board used to derive this data was a 76 mm x 114 mm, 2-layer, 1.6 mm thick PCB with 25 cm² 2-oz copper on
backside.
(3) The JEDEC High-K board used to derive this data was a 76 mm x 114 mm, 4-layer, 1.6 mm thick PCB with no backside copper and
solid 1 oz. internal ground plane.
(4) The JEDEC High-K board used to derive this data was a 76 mm x 114 mm, 4-layer, 1.6 mm thick PCB with 25 cm² 1-oz copper on
backside and solid 1 oz. internal ground plane.
4
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