DRV11873PWPR Datasheet, PDF (4/16 Pages) Texas Instruments – 12-V, 3-PHASE, SENSORLESS BLDC MOTOR DRIVER

DRV11873
SLWS237 – NOVEMBER 2012
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
Input voltage range
Output voltage range
Electrostatic discharge (ESD)
T_J Operating junction temperature
T_stg Storage temperature
VCC
CS
PWMIN, FS, FR
GND
COM
U, V, W
FG, RD
VCP
CPN
CPP
V5
Human body model, HBM
Charge device model, CBM
Machine model, MM
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VALUE
MIN
MAX
-0.3
20
-0.3
3.6
-0.3
6
-0.3
0.3
-1
20
-1
20
-0.3
20
-0.3
25
-0.3
20
-0.3
25
-0.3
6
4
1
200
-40
125
-55
150
UNIT
V
V
kV
V
°C
°C
THERMAL INFORMATION
θ_JA
θ_JCtop
θ_JB
ψ_JT
ψ_JB
θ_JCbot
THERMAL METRIC⁽¹⁾
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case (top) thermal resistance⁽³⁾
Junction-to-board thermal resistance⁽⁴⁾
Junction-to-top characterization parameter⁽⁵⁾
Junction-to-board characterization parameter⁽⁶⁾
Junction-to-case (bottom) thermal resistance⁽⁷⁾
DRV11873
PWP
16 PINS
39.4
30.3
25.6
0.5
10.2
3.6
UNITS
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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