DRV10866 Datasheet, PDF (4/14 Pages) Texas Instruments – 5-V, THREE-PHASE, SENSORLESS BLDC MOTOR DRIVER

DRV10866
SBVS206 – NOVEMBER 2012
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted).
Input voltage range⁽¹⁾
Output voltage range⁽¹⁾
Temperature
Electrostatic discharge (ESD)
VCC
CS, FGS, PWM
GND
COM
U, V, W
FG
Operating junction temperature, T_J
Storage, T_stg
Human body model, HBM
Charge device model, CDM
(1) All voltage values are with respect to network ground terminal unless otherwise noted.
THERMAL INFORMATION
THERMAL METRIC⁽¹⁾
θ_JA
θ_JCtop
θ_JB
ψ_JT
ψ_JB
θ_JCbot
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case (top) thermal resistance⁽³⁾
Junction-to-board thermal resistance⁽⁴⁾
Junction-to-top characterization parameter⁽⁵⁾
Junction-to-board characterization parameter⁽⁶⁾
Junction-to-case (bottom) thermal resistance⁽⁷⁾
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VALUE
MIN
–0.3
–0.3
–0.3
–1.0
–1.0
–0.3
–40
–55
MAX
+6.0
+6.0
+0.3
+6.0
+7.0
+6.0
+125
+150
4
500
UNIT
V
V
V
V
V
V
°C
°C
kV
V
DRV10866
DSC
10 PINS
42.3
44.5
17.1
0.3
17.3
4.3
UNITS
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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