CD74AC02 Datasheet, PDF (4/5 Pages) Texas Instruments – Quad 2-Input NOR Gate

CD74AC02, CD74ACT02
Switching Specifications Input t_r, t_f = 3ns, C_L = 50pF (Worst Case)
-40^oC TO 85^oC
-55^oC TO 125^oC
PARAMETER
AC TYPES
SYMBOL
V_CC (V)
MIN
TYP
MAX
MIN
TYP
MAX UNITS
Propagation Delay, Input to
t_PLH, t_PHL
1.5
-
Output
3.3
4.1
(Note 9)
-
131
-
-
14.6
4
-
144
ns
-
16.1
ns
5
3
(Note 10)
-
10.4
2.9
-
11.5
ns
Input Capacitance
C_I
-
Power Dissipation Capacitance
C_PD
-
(Note 11)
-
-
10
-
-
10
pF
-
55
-
-
55
-
pF
ACT TYPES
Propagation Delay, Input to
Output
t_PLH, t_PHL
5
3.1
(Note 10)
-
11.1
3.1
-
12.2
ns
Input Capacitance
C_I
-
Power Dissipation Capacitance
C_PD
-
(Note 11)
-
-
10
-
-
10
pF
-
55
-
-
55
-
pF
NOTES:
19. Limits tested at 100%.
20. 3.3V Min at 3.6V, Max at 3V.
21. 5V Min at 5.5V, Max at 4.5V.
22. C_PD is used to determine the dynamic power consumption per gate.
AC: P_D = V_CC2 f_i (C_PD + C_L)
ACT: P_D = V_CC2 f_i (C_PD + C_L) + V_CC ∆I_CC where f_i = input frequency, C_L = output load capacitance, V_CC = supply voltage.
OUTPUT
DUT
R_L (NOTE)
500Ω
OUTPUT
LOAD
C_L
50pF
NOTE: For AC Series Only: When V_CC = 1.5V, R_L = 1kΩ.
CD74AC CD74ACT
Input Level
Input Switching Voltage, V_S
Output Switching Voltage, V_S
V_CC
0.5 V_CC
0.5 V_CC
3V
1.5V
0.5 V_CC
FIGURE 2. PROPAGATION DELAY TIMES
t_r = 3ns
INPUT
LEVEL
V_I
V_O
t_f = 3ns
90%
V_S
10% _GND
V_S
t_PHL
t_PLH
FIGURE 3. PROPAGATION DELAY TIMES
4