CD54HC85 Datasheet, PDF (4/15 Pages) Texas Instruments – High-Speed CMOS Logic 4-Bit Magnitude Comparator

CD54HC85, CD74HC85, CD54HCT85, CD74HCT85
DC Electrical Specifications (Continued)
PARAMETER
HCT TYPES
SYMBOL
TEST
CONDITIONS
V_I (V) I_O (mA)
V_CC
(V)
25^oC
-40^oC TO 85^oC -55^oC TO 125^oC
MIN TYP MAX MIN MAX MIN MAX UNITS
High Level Input
Voltage
V_IH
-
-
4.5 to
2
-
-
2
-
2
-
V
5.5
Low Level Input
Voltage
V_IL
-
-
4.5 to
-
-
0.8
-
0.8
-
0.8
V
5.5
High Level Output
V_OH V_IH or V_IL -0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
Low Level Output
Voltage
CMOS Loads
V_OL V_IH or V_IL 0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
4
4.5
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I_I
V_CC and
0
GND
5.5
-
±0.1
-
±1
-
±1
µA
Quiescent Device
Current
I_CC
V_CC or
0
GND
5.5
-
-
8
-
80
-
160
µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I_CC
(Note 2)
V_CC
-2.1
-
4.5 to
-
100 360
-
450
-
490
µA
5.5
NOTE:
2. For dual-supply systems theoretical worst case (V_I = 2.4V, V_CC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
A0-A3, B0-B3 and (A = B) IN
1.5
(A > B) IN, (A < B) IN
1
NOTE:
360µA
mUanxitaLto2a5d^{oiCs.∆ICC}
limit
specified
in
DC
Electrical
Table,
e.g.
Switching Specifications Input t_r, t_f = 6ns
PARAMETER
HC TYPES
Propagation Delay,
A_n, B_n to (A > B) OUT,
(A < B) OUT
A_n, B_n to (A = B) OUT
TEST
25^oC
SYMBOL CONDITIONS V_CC (V) MIN TYP MAX
t_PLH, t_PHL C_L = 50pF
C_L = 15pF
C_L = 50pF
t_PLH, t_PHL C_L = 50pF
C_L = 15pF
C_L = 50pF
2
-
- 195
4.5
-
-
39
5
-
16
-
6
-
-
33
2
-
- 175
4.5
-
-
35
5
-
14
-
6
-
-
30
-40^oC TO
85^oC
MIN MAX
-
245
-
47
-
-
-
42
-
240
-
44
-
-
-
37
-55^oC TO
125^oC
MIN MAX
UNITS
-
295 ns
-
59
ns
-
-
ns
-
50
ns
-
265 ns
-
53
ns
-
-
ns
-
45
ns
4