CD54HC7266_07 Datasheet, PDF (4/12 Pages) Texas Instruments – High-Speed CMOS Logic Quad 2-Input EXCLUSIVE NOR Gate

CD54HC7266, CD74HC7266
DC Electrical Specifications (Continued)
PARAMETER
Input Leakage
Current
TEST
CONDITIONS
SYMBOL
I_I
V_I (V)
V_CC or
GND
I_O (mA)
-
V_CC
(V)
6
Quiescent Device
I_CC
V_CC or
0
6
Current
GND
25^oC
-40^oC TO 85^oC -55^oC TO 125^oC
MIN TYP MAX MIN MAX MIN MAX UNITS
-
-
±0.1
-
±1
-
±1
µA
-
-
2
-
20
-
40
µA
Switching Specifications Input t_r, t_f = 6ns
PARAMETER
HC TYPES
Propagation Delay
TEST
SYMBOL CONDITIONS V_CC (V)
t_PLH, t_PHL C_L = 50pF
2
4.5
25^oC
TYP MAX
-40^oC TO 85^oC -55^oC TO 125^oC
MAX
MAX
UNITS
-
115
145
-
23
29
150
ns
35
ns
6
-
30
25
30
ns
Propagation Delay Time, Any t_PLH, t_PHL C_L = 15pF
5
9
-
-
Input
-
ns
Output Transition Times
t_TLH, t_THL C_L = 50pF
2
-
75
95
(Figure 1)
4.5
-
15
19
110
ns
22
ns
6
-
13
16
19
ns
Input Capacitance
Power Dissipation
Capacitance
C_IN
-
-
-
10
10
C_PD
C_L = 15pF
5
33
-
-
(Note 2)
10
pF
-
pF
NOTE:
2. C_PD is used to determine the dynamic power consumption per gate, P_D = V_CC2 f_i (C_PD + C_L) where f_i = Input Frequency, C_L = Output
Load Capacitance, V_CC = Supply Voltage.
Test Circuit and Waveform
t_r = 6ns
INPUT
90%
50%
10%
t_f = 6ns
V_CC
GND
t_THL
INVERTING
OUTPUT
t_PHL
t_TLH
90%
50%
10%
t_PLH
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
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