CD54HC534 Datasheet, PDF (4/14 Pages) Texas Instruments – High-Speed CMOS Logic Octal D-Type Flip-Flop, Three-State Inverting Positive-Edge Triggered

CD54/74HC534, CD54/74HCT534, CD54/74HC564, CD54/74HCT564
DC Electrical Specifications (Continued)
PARAMETER
Quiescent Device
Current
SYMBOL
I_CC
TEST
CONDITIONS
V_I (V)
V_CC or
GND
I_O (mA)
0
V_CC
(V)
6
25^oC
-40^oC TO 85^oC -55^oC TO 125^oC
MIN TYP MAX MIN MAX MIN MAX UNITS
-
-
8
-
80
-
160
µA
Three- State Leakage V_IL or V_IH V_O = V_CC
-
Current
or GND
6
-
-
±0.5
-
±5.0
-
±10
µA
HCT TYPES
High Level Input
Voltage
V_IH
-
-
4.5 to
2
-
-
2
-
2
-
V
5.5
Low Level Input
Voltage
V_IL
-
-
4.5 to
-
-
0.8
-
0.8
-
0.8
V
5.5
High Level Output
V_OH V_IH or V_IL -0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
-6
4.5
3.98
-
-
3.84
-
3.7
-
V
Low Level Output
Voltage
CMOS Loads
V_OL V_IH or V_IL 0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
6
4.5
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I_I
V_CC and
0
GND
5.5
-
±0.1
-
±1
-
±1
µA
Quiescent Device
Current
I_CC
V_CC or
0
GND
5.5
-
-
8
-
80
-
160
µA
Three- State Leakage V_IL or V_IH V_O = V_CC
-
Current
or GND
5.5
-
-
±0.5
-
±5.0
-
±10
µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I_CC
(Note 2)
V_CC
-2.1
-
4.5 to
-
100 360
-
450
-
490
µA
5.5
NOTE:
2. For dual-supply systems theoretical worst case (V_I = 2.4V, V_CC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
D0 - D7
0.15
CP
0.30
OE
0.55
NOTE: Unit Load is ∆I_CC limit specific in DC Electrical Specifications
Table, e.g., 360µA max. at 25^oC.
4