CD54HC4049_07 Datasheet, PDF (4/10 Pages) Texas Instruments – High-Speed CMOS Logic Hex Buffers, Inverting and Non-Inverting

CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050
DC Electrical Specifications (Continued)
PARAMETER
Quiescent Device
Current
SYMBOL
I_CC
TEST
CONDITIONS
V_I (V)
V_CC or
GND
I_O (mA)
0
V_CC
(V)
6
25^oC
–40^oC TO 85^oC
–55^oC TO
125^oC
MIN TYP MAX MIN MAX MIN MAX UNITS
-
-
2
-
20
-
40
µA
Switching Specifications Input t_r, t_f = 6ns
PARAMETER
HC TYPES
Propagation Delay,
nA to nY HC4049
nA to nY HC4050
TEST
25^oC
SYMBOL CONDITIONS V_CC (V) MIN TYP MAX
t_PLH, t_PHL C_L = 50pF
2
-
-
85
4.5
-
-
17
6
-
-
14
–40^oC TO
85^oC
MIN MAX
-
105
-
21
-
18
–55^oC TO
125^oC
MIN MAX
-
130
-
26
-
22
C_L = 15pF
5
-
6
-
-
-
-
-
Transition Times (Figure 1)
t_TLH, t_THL C_L = 50pF
2
-
-
75
-
95
-
110
4.5
-
-
15
-
19
-
22
6
-
-
13
-
16
-
19
Input Capacitance
C_I
-
Power Dissipation Capacitance C_PD
-
(Notes 2, 3)
-
-
-
10
-
10
-
10
5
-
35
-
-
-
-
-
NOTES:
2. C_PD is used to determine the dynamic power consumption, per gate.
3. P_D = V_CC2 f_i (C_PD + C_L) where f_i = Input Frequency, C_L = Output Load Capacitance, V_CC = Supply Voltage.
UNITS
ns
ns
ns
ns
ns
ns
ns
pF
pF
Test Circuit and Waveform
t_r = 6ns
INPUT
90%
50%
10%
t_f = 6ns
V_CC
GND
t_THL
INVERTING
OUTPUT
t_PHL
t_TLH
90%
50%
10%
t_PLH
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
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