CD54HC4015_07 Datasheet, PDF (4/10 Pages) Texas Instruments – High Speed CMOS Logic Dual 4-Stage Static Shift Register

CD54HC4015, CD74HC4015
Prerequisite for Switching Specifications
PARAMETER
Maximum Clock
Frequency
Clock Pulse Width
MR Pulse Width
MR Recovery Time
Set-up Time,
Data-In to CP
Hold Time,
Data-In to CP
SYMBOL
f_MAX
t_W
t_W
t_REC
t_SUL, t_SUH
t_H
V_CC (V)
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
2
4.5
6
25^oC
MIN
MAX
6
-
30
-
35
-
80
-
16
-
14
-
150
-
30
-
26
-
50
-
10
-
9
-
60
-
12
-
10
-
0
-
0
-
0
-
-40^oC TO 85^oC
MIN
MAX
5
-
24
-
28
-
100
-
20
-
17
-
190
-
38
-
33
-
65
-
13
-
11
-
75
-
15
-
13
-
0
-
0
-
0
-
-55^oC TO 125^oC
MIN
MAX
4
-
20
-
24
-
120
-
24
-
20
-
225
-
45
-
38
-
75
-
15
-
13
-
90
-
18
-
15
-
0
-
0
-
0
-
UNITS
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching Specifications Input t_r, t_f = 6ns
PARAMETER
TEST
SYMBOL CONDITIONS
V_CC
(V)
25^oC
-40^oC TO 85^oC -55^oC TO 125^oC
MIN TYP MAX MIN MAX MIN MAX UNITS
Propagation Delay (Figure 1)
Clock to Q_n
MR to Q_n, (Clock High)
t_PLH,
t_PHL
t_PLH,
t_PHL
C_L = 50pF
C_L =15pF
C_L = 50pF
C_L = 50pF
2
-
- 175
-
4.5
-
-
35
-
5
-
14
-
-
6
-
-
30
-
2
-
- 275
-
4.5
-
-
55
-
220
-
270
ns
44
-
54
ns
-
-
-
ns
37
-
46
ns
345
-
415
ns
64
-
83
ns
MR to Q_n, (Clock Low)
t_PLH,
t_PHL
C_L =15pF
C_L = 50pF
C_L = 50pF
25
-
-
6
-
-
47
-
2
-
- 325
-
4.5
-
-
65
-
-
-
-
ns
54
-
71
ns
400
-
490
ns
81
-
98
ns
Output Transition Time
(Figure 1)
C_L =15pF
C_L = 50pF
t_TLH, t_THL C_L = 50pF
25
-
-
6
-
-
55
-
2
-
-
75
-
4.5
-
-
15
-
-
-
-
ns
69
-
83
ns
95
-
110
ns
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Input Capacitance
Maximum Clock Frequency
Power Dissipation
Capacitance
(Notes 2, 3)
C_IN
f_MAX
C_PD
C_L = 50pF
C_L =15pF
C_L =15pF
-
-
-
10
-
10
-
10
pF
5
-
60
-
-
-
-
-
MHz
5
-
43
-
-
-
-
-
pF
NOTES:
2. C_PD is used to determine the dynamic power consumption, per shift register.
3. P_D = V_CC2 f_i + ∑ C_L V_CC2 where f_i = Input Frequency, C_L = Output Load Capacitance, V_CC = Supply Voltage.
4