CD54HC280_07 Datasheet, PDF (4/12 Pages) Texas Instruments – High-Speed CMOS Logic 9-Bit Odd/Even Parity Generator/Checker

CD54HC280, CD74HC280, CD54HCT280, CD74HCT280
Switching Specifications Input t_r, t_f = 6ns (Continued)
PARAMETER
Output Transition Time
SYMBOL
t_TLH, t_THL
TEST
CONDITIONS V_CC (V)
C_L = 50pF
2
4.5
25^oC
-40^oC TO 85^oC
TYP MAX
MAX
-
75
95
-
15
19
-55^oC TO
125^oC
MAX
110
22
UNITS
ns
ns
6
-
13
16
19
ns
Input Capacitance
Power Dissipation
Capacitance
(Notes 3, 4)
C_I
-
-
-
10
10
C_PD
-
5
58
-
-
10
pF
-
pF
HCT TYPES
Propagation Delay,
Any Input to ΣO
t_PLH, t_PHL C_L = 50pF
4.5
-
45
56
C_L = 15pF
5
19
-
-
Propagation Delay,
Any Input to ΣE
t_PLH, t_PHL C_L = 50pF
4.5
-
42
53
C_L = 15pF
5
18
-
-
Output Transition Time
t_TLH, t_THL C_L = 50pF
4.5
-
15
19
Input Capacitance
C_IN
-
-
-
10
10
Power Dissipation
Capacitance
(Notes 3, 4)
C_PD
-
5
58
-
-
68
ns
-
ns
63
ns
-
ns
22
ns
10
pF
-
pF
NOTES:
3. C_PD is used to determine the dynamic power consumption, per package.
4. P_D = V_CC2 f_i (C_PD + C_L) where f_i = Input Frequency, f_O = Output Frequency, C_L = Output Load Capacitance, V_CC = Supply Voltage.
Test Circuits and Waveforms
t_r = 6ns
INPUT
90%
50%
10%
t_f = 6ns
V_CC
GND
t_THL
INVERTING
OUTPUT
t_PHL
t_TLH
90%
50%
10%
t_PLH
FIGURE 1. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
t_r = 6ns
INPUT
t_THL
2.7V
1.3V
0.3V
INVERTING
OUTPUT
t_PHL
t_f = 6ns
3V
GND
t_TLH
90%
1.3V
10%
t_PLH
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
4