CD54HC126_08 Datasheet, PDF (4/14 Pages) Texas Instruments – High-Speed CMOS Logic Quad Buffer, Three-State

CD54HC126, CD74HC126, CD54HCT126, CD74HCT126
DC Electrical Specifications (Continued)
PARAMETER
Quiescent Device
Current
Three-State Leakage
Current
HCT TYPES
High Level Input
Voltage
TEST
CONDITIONS
25^oC
SYMBOL V_I (V) I_O (mA) V_CC (V) MIN
I_CC
V_CC or
0
GND
6
-
TYP MAX
-
8
I_OZ
V_IL or
-
V_IH
6
-
- ±0.5
V_IH
-
-
4.5 to 2
-
-
5.5
-40^oC TO 85^oC
MIN MAX
-
80
-
±5
2
-
Low Level Input
Voltage
V_IL
-
-
4.5 to -
- 0.8
-
0.8
5.5
High Level Output
Voltage
CMOS Loads
V_OH
V_IH or -0.02
4.5
4.4
-
-
4.4
-
V_IL
High Level Output
Voltage
TTL Loads
-6
4.5 3.98 -
-
3.84
-
Low Level Output
Voltage
CMOS Loads
V_OL
V_IH or 0.02
4.5
-
- 0.1
-
0.1
V_IL
Low Level Output
Voltage
TTL Loads
6
4.5
-
- 0.26
-
0.33
Input Leakage
Current
I_I
V_CC to
0
5.5
-
- ±0.1
-
±1
GND
Quiescent Device
Current
I_CC
V_CC or
0
5.5
-
-
8
-
80
GND
Additional Quiescent
∆I_CC
V_CC
-
4.5 to - 100 360
-
450
Device Current Per
(Note 2) -2.1
5.5
Input Pin: 1 Unit Load
Three-State Leakage
I_OZ
V_IL or
-
5.5
-
- ±0.5
-
±5
Current
V_IH
NOTE:
2. For dual-supply systems theoretical worst case (V_I = 2.4V, V_CC = 5.5V) specification is 1.8mA.
-55^oC TO 125^oC
MIN MAX UNITS
-
160
µA
-
±10
µA
2
-
V
-
0.8
V
4.4
-
V
3.7
-
V
-
0.1
V
-
0.4
V
-
±1
µA
-
160
µA
-
490
µA
-
±10
µA
HCT Input Loading Table
INPUT
UNIT LOADS
nA, nOE
1
NOTE: Unit Load is ∆I_CC limit specified in DC Electrical
Specifications table, e.g., 360µA max at 25^oC.
4