CD54HC109 Datasheet, PDF (4/12 Pages) Texas Instruments – Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

CD54HC109, CD74HC109, CD54HCT109, CD74HCT109
DC Electrical Specifications (Continued)
PARAMETER
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
HCT TYPES
High Level Input
Voltage
TEST
CONDITIONS
25^oC
SYMBOL
V_OL
V_I (V)
V_IH or
V_IL
I_O (mA) V_CC (V) MIN
0.02
2
-
4.5
-
TYP MAX
- 0.1
- 0.1
6
-
- 0.1
-
-
-
-
-
4
4.5
-
- 0.26
5.2
6
-
- 0.26
I_I
V_CC or
-
GND
6
-
- ±0.1
I_CC
V_CC or
0
GND
6
-
-
4
-40^oC TO 85^oC
MIN MAX
-
0.1
-
0.1
-
0.1
-
-
-
0.33
-
0.33
-
±1
-
40
V_IH
-
-
4.5 to 2
-
-
2
-
5.5
Low Level Input
Voltage
V_IL
-
-
4.5 to -
- 0.8
-
0.8
5.5
High Level Output
Voltage
CMOS Loads
V_OH
V_IH or -0.02
4.5
4.4
-
-
4.4
-
V_IL
High Level Output
Voltage
TTL Loads
-4
4.5 3.98 -
-
3.84
-
Low Level Output
V_OL
V_IH or 0.02
4.5
-
- 0.1
-
0.1
Voltage CMOS Loads
V_IL
Low Level Output
Voltage
TTL Loads
4
4.5
-
- 0.26
-
0.33
Input Leakage
Current
I_I
V_CC
-
5.5
-
and
GND
±0.1
-
±1
Quiescent Device
Current
I_CC
V_CC or
0
5.5
-
-
4
-
40
GND
Additional Quiescent
∆I_CC
V_CC
-
4.5 to - 100 360
-
450
Device Current Per
(Note 3) - 2.1
5.5
Input Pin: 1 Unit Load
NOTE:
3. For dual-supply systems theoretical worst case (V_I = 2.4V, V_CC = 5.5V) specification is 1.8mA.
-55^oC TO 125^oC
MIN MAX UNITS
-
0.1
V
-
0.1
V
-
0.1
V
-
-
V
-
0.4
V
-
0.4
V
-
±1
µA
-
80
µA
2
-
V
-
0.8
V
4.4
-
V
3.7
-
V
-
0.1
V
-
0.4
V
-
±1
µA
-
80
µA
-
490
µA
HCT Input Loading Table
INPUT
UNIT LOADS
All
0.3
NOTE: Unit Load is ∆I_CC limit
tions table, e.g., 360µA max at
specified
25^oC.
in
DC
Electrical
Specifica-
4