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CD54AC112_06 Datasheet, PDF (4/11 Pages) Texas Instruments – DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET | |||
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CD54AC112, CD74AC112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS325 â JANUARY 2003
timing requirements over recommended operating free-air temperature range, VCC = 1.5 V (unless
otherwise noted)
fclock Clock frequency
tw
Pulse duration
tsu
Setup time, before CLKâ
th
Hold time, after CLKâ
trec
Recovery time, before CLKâ
CLK high or low
CLR or PRE low
J or K
J or K
CLRâ or PREâ
â55°C to
125°C
MIN MAX
8
63
56
50
0
31
â40°C to
85°C
MIN MAX
9
55
49
44
0
27
UNIT
MHz
ns
ns
ns
ns
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted)
fclock Clock frequency
tw
Pulse duration
tsu
Setup time, before CLKâ
th
Hold time, after CLKâ
trec
Recovery time, before CLKâ
CLK high or low
CLR or PRE low
J or K
J or K
CLRâ or PREâ
â55°C to
125°C
MIN MAX
71
7
6.3
5.6
0
3.5
â40°C to
85°C
MIN MAX
81
6
5.5
4.9
0
3..1
UNIT
MHz
ns
ns
ns
ns
timing requirements over recommended operating free-air temperature0 range, VCC = 5 V ± 0.5 V
(unless otherwise noted)
fclock Clock frequency
tw
Pulse duration
tsu
Setup time, before CLKâ
th
Hold time, after CLKâ
trec
Recovery time, before CLKâ
CLK high or low
CLR or PRE low
J or K
J or K
CLRâ or PREâ
â55°C to
125°C
MIN MAX
100
5
4.5
4
0
2.5
â40°C to
85°C
MIN MAX
114
4.4
3.9
3.5
0
2.2
UNIT
MHz
ns
ns
ns
ns
4
⢠POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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