ADS5413-11 Datasheet, PDF (4/19 Pages) Texas Instruments – SINGLE 11-BIT, 65-MSPS HIGH IF SAMPLING

ADS5413-11
SLWS156 − MARCH 2004
www.ti.com
ELECTRICAL CHARACTERISTICS (CONTINUED)
over operating free-air temperature range, clock frequency = 65 MSPS, 50% clock duty cycle (AVDD = OVDD = 3.3 V), duty cylce adjust off,
internal reference, AIN = −1 dBFS, 1.2-VPP square differential clock (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
AC PERFORMANCE (Continued)
SFDR Spurious free dynamic range
HD2 Second order harmonic
HD3 Third order harmonic
Analog input bandwidth
fIN = 14 MHz
fIN = 39 MHz
fIN = 70 MHz
fIN = 150 MHz
fIN = 190 MHz
fIN = 220 MHz
fIN = 14 MHz
fIN = 39 MHz
fIN = 70 MHz
fIN = 150 MHz
fIN = 190 MHz
fIN = 220 MHz
fIN = 14 MHz
fIN = 39 MHz
fIN = 70 MHz
fIN = 150 MHz
fIN = 190 MHz
fIN = 220 MHz
−3 dB BW respect to −3 dBFS input at low
frequency
70 77.7
75.8
84.5
70.5
68.3
72.9
95
94
89
79
84.5
72
77.6
75.4
85.5
70.5
68.3
77.6
1
dBc
dBc
dBc
GHz
TIMING CHARACTERISTICS
25°C, CL = 10 pF
td(A)
Aperture delay
Aperture jitter
td(Pipe) Latency
td1
Propagation delay from clock input to beginning of data stable(1)
td2
Propagation delay from clock input to end of data stable(1)
td1
Propagation delay from clock input to beginning of data stable(1)
td2
Propagation delay from clock input to end of data stable(1)
td1
Propagation delay from clock input to beginning of data stable(1)
td2
Propagation delay from clock input to end of data stable(1)
td1
Propagation delay from clock input to beginning of data stable(1)
td2
Propagation delay from clock input to end of data stable(1)
(1) _{Data stable if VO < 10% OVDD or VO > 90% OVDD}
DCS off, OVDD = 1.8 V
DCS off, OVDD = 3.3 V
DCS on, OVDD = 1.8 V
DCS on, OVDD = 3.3 V
MIN TYP MAX UNIT
2
ns
0.4
ps
6
Cycles
8
ns
20.3
7
ns
20.3
10
ns
22.3
9
ns
22.3
4