ADC083000CIYBNOPB Datasheet, PDF (4/48 Pages) Texas Instruments – ADC083000 8-Bit, 3 GSPS, High Performance, Low Power A/D Converter

ADC083000
SNAS358N – JUNE 2006 – REVISED JULY 2009
Pin Functions
Pin No.
Symbol
Pin Descriptions and Equivalent Circuits
Equivalent Circuit
Description
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3
OutV / SCLK
V_A
50k
GND
Output Voltage Amplitude / Serial Interface Clock
(Input):LVCMOS Tie this pin high for normal differential DCLK and
data amplitude. Ground this pin for a reduced differential output
amplitude and reduced power consumption. See The LVDS
Outputs. When the extended control mode is enabled, this pin
functions as the SCLK input which clocks in the serial data. See
NORMAL/EXTENDED CONTROL for details on the extended
control mode. See THE SERIAL INTERFACE for description of the
serial interface.
V_A
4
OutEdge / DDR /
SDATA
50k
200k
50k 8 pF
GND
DDR
SDATA
Edge Select / Double Data Rate / Serial Data
(Input):LVCMOS This input sets the output edge of DCLK+ at
which the output data transitions. (See OutEdge Setting). When
this pin is floating or connected to 1/2 the supply voltage, DDR
clocking is enabled. When the extended control mode is enabled,
this pin functions as the SDATA input. See NORMAL/EXTENDED
CONTROL for details on the extended control mode. See THE
SERIAL INTERFACE for description of the serial interface.
15
DCLK_RST
26
PD
30
CAL
14
FSR/ECE
127
CalDly / SCS
V_A
V_A
GND
V_A
50k
200k
50k 8 pF
GND
V_A
50k
50k
GND
DCLK Reset
(Input):LVCMOS A positive pulse on this pin is used to reset and
synchronize the DCLK outs of multiple converters. See MULTIPLE
ADC SYNCHRONIZATION for detailed description. When bit 14 in
the Configuration Register (address 1h) is set to 0b, this single-
ended DCLK_RST pin is selected. See also pins 22,23 description.
Power Down
(Input):LVCMOS A logic high on the PD pin puts the entire device
into the Power Down Mode.
Calibration Cycle Initiate
(Input):LVCMOS A minimum 80 input clock cycles logic low
followed by a minimum of 80 input clock cycles high on this pin
initiates the calibration sequence. See Calibration for an overview
of self-calibration and On-Command Calibration for a description of
on-command calibration.
Full Scale Range Select / Extended Control Enable
(Input):LVCMOS In non-extended control mode, a logic low on this
pin sets the full-scale differential input range to 600 mV_P-P. A logic
high on this pin sets the full-scale differential input range to 820
mV_P-P. See The Analog Inputs. To enable the extended control
mode, whereby the serial interface and control registers are
employed, allow this pin to float or connect it to a voltage equal to
V_A/2. See NORMAL/EXTENDED CONTROL for information on the
extended control mode.
Calibration Delay / Serial Interface Chip Select
(Input):LVCMOS With a logic high or low on pin 14, this pin
functions as Calibration Delay and sets the number of input clock
cycles after power up before calibration begins (See Calibration).
With pin 14 floating, this pin acts as the enable pin for the serial
interface input and the CalDly value becomes "0" (short delay with
no provision for a long power-up calibration delay).
4
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