AD7724AST-REEL Datasheet, PDF (4/16 Pages) Analog Devices – Dual CMOS
- Modulators

AD7724
TIMING CHARACTERISTICS^{1, 2 (AVDD = 5 V ؎ 5%; DVDD = 5 V ؎ 5%; DVDD1 = 3 V ؎ 5%; AGND = DGND = 0 V, REF2A =}
REF2B = 2.5 V, unless otherwise noted.)
Parameter
Limit at T_MIN, T_MAX
(A Version)
Unit
Conditions/Comments
f_MCLK
t_DELAY
t₁
t₂
t₃
t₄
t₅
t₆
t₇
t₈
t₉
100
15
14
67
0.45 × t_MCLK
0.45 × t_MCLK
15
10
10
20 × t_MCLK
3
t₃–t₈
NOTES
1_{Sample tested at 25°C to ensure compliance.}
2_{Guaranteed by design.}
kHz min
MHz max
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns max
Master Clock Frequency
13 MHz for Specified Performance
MCLK to SCLK Delay
Master Clock Period
Master Clock Input High Time
Master Clock Input Low Time
Data Hold Time After SCLK Rising Edge
RESET Pulsewidth
RESET Low Time Before MCLK Rising
DVAL High Delay After RESET Low
Data Access Time After SCLK Falling Edge
Data Valid Time Before SCLK Rising Edge
SCLK (O)
DATA (O)
I_OL
1.6mA
TO
OUTPUT
PIN
C_L
50pF
1.6V
I_OH
200␮A
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
t₁
t₂
t₃
t₈
t₄
t₉
NOTE:
O SIGNIFIES AN OUTPUT
Figure 3. Data Timing
MCLK (I)
t₆
RESET (I)
t₅
t₇
DVAL (O)
NOTE:
I SIGNIFIES AN INPUT
O SIGNIFIES AN OUTPUT
Figure 4. RESET Timing
–4–
REV. B