TMS320VC5410PGE100 Datasheet, PDF (39/84 Pages) Texas Instruments – TMS320VC5410 Fixed-Point Digital Signal Processor

Functional Overview
2.2.9.9 DMA Interrupts
The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is
determined by the IMOD and DINM bits in the DMA channel mode control register (DMMCRn). The available
modes are shown in Table 2--6.
MODE
ABU (non-decrement)
ABU (non-decrement)
Multi-Frame
Multi-Frame
Either
Either
DINM
1
1
1
1
0
0
Table 2--6. DMA Interrupts
IMOD
INTERRUPT
0
At full buffer only
1
At half buffer and full buffer
0
At block transfer complete (DMCTRn = DMSEFCn[7:0] = 0)
1
At end of frame and end of block (DMCTRn = 0)
X
No interrupt generated
X
No interrupt generated
October 1998 -- December 2000
SPRS075E
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