TAS5731_15 Datasheet, PDF (39/59 Pages) Texas Instruments – 2 × 20-W DIGITAL AUDIO POWER AMPLIFIER WITH DSP AND 2.1 MODE

TAS5731
www.ti.com
SLOS726A – DECEMBER 2011 – REVISED SEPTEMBER 2013
ERROR STATUS REGISTER (0x02)
The error bits are sticky and are not cleared by the hardware. This means that the software must clear the
register (write zeroes) and then read them to determine if they are persistent errors.
Error Definitions:
• MCLK Error : MCLK frequency is changing. The number of MCLKs per LRCLK is changing.
• SCLK Error: The number of SCLKs per LRCLK is changing.
• LRCLK Error: LRCLK frequency is changing.
• Frame Slip: LRCLK phase is drifting with respect to internal Frame Sync.
D7 D6 D5 D4 D3
1
-
–
–
–
–
1
–
–
–
–
–
1
–
–
–
–
–
1
–
–
–
–
–
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
(1) Default values are in bold.
Table 6. Error Status Register (0x02)
D2
D1
D0
FUNCTION
–
–
– MCLK error
–
–
– PLL autolock error
–
–
– SCLK error
–
–
– LRCLK error
–
–
– Frame slip
1
–
– Clip indicator
–
1
– Overcurrent, overtemperature, or undervoltage errors
–
–
0 Reserved
0
0
– No errors ⁽¹⁾
SYSTEM CONTROL REGISTER 1 (0x03)
The system control register 1 has several functions:
Bit D7:
If 0, the dc-blocking filter for each channel is disabled.
If 1, the dc-blocking filter (–3 dB cutoff <1 Hz) for each channel is enabled (default).
Bit D5:
If 0, use soft unmute on recovery from clock error. This is a slow recovery. Unmute takes the
same time as the volume ramp defined in register 0x0E.
If 1, use hard unmute on recovery from clock error (default). This is a fast recovery, a single step
volume ramp
Bits D1–D0: Select de-emphasis
D7 D6 D5 D4 D3
0
–
–
–
–
1
–
–
–
–
–
0
–
–
–
–
–
0
–
–
–
–
1
–
–
–
–
–
0
–
–
–
–
–
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(1) Default values are in bold.
Table 7. System Control Register 1 (0x03)
D2
D1
D0
FUNCTION
–
–
– PWM high-pass (dc blocking) disabled
–
–
– PWM high-pass (dc blocking) enabled ⁽¹⁾
–
–
– Reserved ⁽¹⁾
–
–
– Soft unmute on recovery from clock error
–
–
– Hard unmute on recovery from clock error ⁽¹⁾
–
–
– Reserved ⁽¹⁾
–
–
– Reserved ⁽¹⁾
0
–
– Reserved⁽¹⁾
–
0
0 No de-emphasis ⁽¹⁾
–
0
1 De-emphasis for f_S = 32 kHz
–
1
0 De-emphasis for f_S = 44.1 kHz
–
1
1 De-emphasis for f_S = 48 kHz
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