TRF3722_15 Datasheet, PDF (38/67 Pages) Texas Instruments – TRF3722 Quadrature Modulator with Integrated PLL and VCO

TRF3722
SLWS245A – MAY 2014 – REVISED JUNE 2014
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Feature Description (continued)
Frac-N performance data is obtained using the fractional loop filter shown in Figure 134. 40 kHz loop bandwidth
and 15.36 MHz PFD was considered.
CP_OUT
VTUNE
C2
10nF
R3
1.1K
R4
1.1K
C1
1nF
R2
1.1K
C3
330pF
C4
330pF
Figure 134. Fractional Loop Filter
9.3.7 Lock Detect
The lock detect signal is generated in the phase frequency detector by comparing the two input signals. When
the two compared phase signals remain aligned for several clock cycles, an internal signal goes high. The
precision of this comparison is controlled through the LD_ANA_PREC bits. This internal signal is then averaged
and compared against a reference voltage to generate the lock detect (LD) signal. The number of averages used
is controlled through LD_DIG_PREC. Therefore, when the VCO is frequency locked, LD is high. When the VCO
frequency is not locked, LD may pulse high or exhibit periodic behavior.
By default, the internal lock detect signal is made available on the LD terminal. Register bits MUX_CTRL can be
used to control a multiplexer to output other diagnostic signals on the LD output.
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