ADS5525 Datasheet, PDF (38/48 Pages) Texas Instruments – 12-BIT, 170 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

ADS5525
SLWS191 – JULY 2006
www.ti.com
Table 11. LVDS Buffer Currents Programming
REGISTER ADDRESS
REGISTER DATA
DESCRIPTION
A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
<LVDS CURRENT> – Output data and clock buffers current programmability
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0 3.5 mA ^{Default after reset}
0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 2.5 mA
0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 4.5 mA
0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1.75 mA
<CURRENT DOUBLE> – The output data and clock buffer currents are doubled from the value selected by the <LVDS CURRENT>
register.
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Value specified by <LVDS
CURRENT>^{Default after reset}
0 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 2x data, 2x clock currents
0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1x data, 2x clock currents
0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 2x data, 4x clock currents
LVDS Buffer Internal Termination
An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially
terminated inside the device. The termination resistances available are – 325, 200, and 170 Ω (nominal with
±20% variation). Any combination of these three terminations can be programmed; the effective termination is
the parallel combination of the selected resistances. This results in eight effective terminations from open (no
termination) to 75 Ω.
The internal termination helps to absorb any reflections coming from the receiver end, improving the signal
integrity. With 100-Ω internal and 100-Ω external termination, the voltage swing at the receiver end is halved
(compared to no internal termination). The voltage swing can be restored by using the LVDS current double
mode (see Table 11).
Table 12. Programming Internal Termination for LVDS Data and Clock
REGISTER ADDRESS
REGISTER DATA
DESCRIPTION
A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
<DATA TERM> Internal termination - Option to terminate the LVDS DATA buffers inside the ADC to improve signal integrity. By
default, internal termination is disabled.
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0 No termination ^{Default after reset}
0 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 325 Ω
0 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 200 Ω
0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 125 Ω
0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 170 Ω
0 1 1 1 1 1 1 0 1 0 1 0 0 0 0 0 120 Ω
0 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 100 Ω
0 1 1 1 1 1 1 0 1 1 1 0 0 0 0 0 75 Ω
<CLK TERM> Internal termination – Option to terminate the LVDS CLK buffers inside the ADC to improve signal integrity. By
default, internal termination is disabled.
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0 No termination ^{Default after reset}
0 1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 325 Ω
0 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 200 Ω
0 1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 125 Ω
0 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 170 Ω
0 1 1 1 1 1 1 0 0 0 0 1 0 1 0 0 120 Ω
0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 100 Ω
0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 75 Ω
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