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TMS370CX0X Datasheet, PDF (37/49 Pages) Texas Instruments – 8-BIT MICROCONTROLLER | |||
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TMS370Cx0x
8-BIT MICROCONTROLLER
SPNS029C â SEPTEMBER 1995 â REVISED FEBRUARY 1997
Table 17. Peripheral File Frame Compilation (Continued)
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ PF
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ Modes: Dual-Compare and Capture/Compare (Continued)
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P044 Bit15
Capture/Compare Register MSbyte
P045 Bit 7
Capture/Compare Register LSbyte
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P046 Bit15
Watchdog Counter MSbyte
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P047 Bit7
Watchdog Counter LSbyte
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P048 Bit7
Watchdog Reset Key
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P049
WD OVRFL
TAP SELâ
WD INPUT
SELECT2â
WD INPUT
SELECT1â
WD INPUT
SELECT0â
â
T1 INPUT
SELECT2
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P04A
WD OVRFL
RST ENAâ
WD OVRFL
INT ENA
WD OVRFL
INT FLAG
T1 OVRFL
INT ENA
T1 OVRFL
INT FLAG
â
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ Mode: Dual-Compare
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P04B
T1EDGE
INT FLAG
T1C2
INT FLAG
T1C1
INT FLAG
â
â
T1EDGE
INT ENA
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P04C T1MODE=0
T1C1
OUT ENA
T1C2
OUT ENA
T1C1
RST ENA
T1CR
OUT ENA
T1EDGE
POLARITY
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ Mode: Capture / Compare
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P04B
T1EDGE
INT FLAG
â
T1C1
INT FLAG
â
â
T1EDGE
INT ENA
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P04C
T1
MODE = 1
T1C1
OUT ENA
â
T1C1
RST ENA
â
T1EDGE
POLARITY
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ Modes: Dual-Compare and Capture/Compare
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P04D
â
â
â
â
T1EVT
DATA IN
T1EVT
DATA OUT
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P04E
T1PWM
DATA IN
T1PWM
DATA OUT
T1PWM
FUNCTION
T1PWM
DATA DIR
T1IC/CR
DATA IN
T1IC/CR
DATA OUT
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P04F T1STEST
T1
PRIORITY
â
â
â
â
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ SCI1 Module Control Memory Map
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P050 STOPBITS
EVEN/ODD
PARITY
PARITY
ENABLE
ASYNC/
ISOSYNC
ADDRESS/
IDLE WUP
SCI CHAR2
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P051
â
â
SCI SW
RESET
CLOCK
TXWAKE
SLEEP
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P052
BAUDF
(MSB)
BAUDE
BAUDD
BAUDC
BAUDB
BAUDA
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P053 BAUD7
BAUD6
BAUD5
BAUD4
BAUD3
BAUD2
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P054 TXRDY
TX EMPTY
â
â
â
â
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P055
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P056
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P057
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P058
RX
ERROR
RXDT7
RXRDY
RXDT6
BRKDT
RXDT5
FE
OE
Reserved
RXDT4
RXDT3
Reserved
PE
RXDT2
BIT 1
T1 INPUT
SELECT1
â
T1C2
INT ENA
T1CR
RST ENA
â
â
T1EVT
FUNCTION
T1IC/CR
FUNCTION
â
SCI CHAR1
TXENA
BAUD9
BAUD1
â
RXWAKE
RXDT1
BIT 0
REG
Bit 8 T1CC
Bit 0
Bit 8 WDCNTR
Bit 0
Bit 0 WDRST
T1 INPUT
SELECT0
T1CTL1
T1
SW RESET
T1CTL2
T1C1
INT ENA
T1EDGE
DET ENA
T1CTL3
T1CTL4
T1C1
INT ENA
T1EDGE
DET ENA
T1CTL3
T1CTL4
T1EVT
DATA DIR
T1PC1
T1IC/CR DATA
DIR
T1PC2
â
T1PRI
SCI CHAR0 SCICCR
RXENA
SCICTL
BAUD8
BAUD MSB
BAUD0 (LSB)
SCI TX
INT ENA
SCI RX
INT ENA
BAUD LSB
TXCTL
RXCTL
RXDT0
RXBUF
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ â Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard
watchdog and to simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2
bits are ignored.
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