ADS8327_13 Datasheet, PDF (37/50 Pages) Texas Instruments – LOW POWER, 16-BIT, 500-kHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE

ADS8327
ADS8328
www.ti.com
SLAS415E – APRIL 2006 – REVISED JANUARY 2011
When the device is powered up, the POR sets the device in default mode when AVDD reaches 1.5 V. When the
device is powered down, the POR circuit requires AVDD to remain below 125 mV for a duration of at least 350
ms to ensure proper discharging of internal capacitors and to correct the behavior of the device when powered
up again. If AVDD drops below 400 mV but remains above 125 mV, the internal POR capacitor does not
discharge fully and the device requires a software reset to perform correctly after the recovery of AVDD (this is
shown as the undefined zone in Figure 65).
AVDD (V)
5.500
5.000
4.000
Specified Supply
Voltage Range
3.000
2.700
2.000
1.500
1.000
POR
Trigger Level
0.400
0.125
Undefined Zone
0
0.350
t (s)
Figure 65. Relevant Voltage Levels for POR
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