TPS65040_07 Datasheet, PDF (36/74 Pages) Texas Instruments – CLOCK- AND POWER-MANAGEMENT IC FOR RF SYSTEM

TPS65040
SLVS708B – NOVEMBER 2006 – REVISED APRIL 2007
CLOCK DISTRIBUTION/SIN_SYSCLK2 INPUT
vs
OUTPUT (–1 dB TYP)
VBAT = 3.8 V,
C_L2 = 10 pF,
R_L2 = 10 kW
SYSCLK_IN
500 mV/div
SIN_SYSCLK2
500 mV/div
10 ns/div
Figure 41.
CLOCK DISTRIBUTION/SIN_SYSCLK3 INPUT
vs
OUTPUT (–1 dB TYP)
CLOCK DISTRIBUTION/SIN_SYSCLK3
STARTUP TIME
VTCXO level
OFF
0V
VBAT = 3.8 V,
C_L3 = 10 pF,
R_L3 = 10 kW
ON
SIN_SYSCLK3
1 V/div
WRFON
1 V/div
40 ns/div
Figure 42.
SYSCLK_IN (VCTCXO OUTPUT)
INPUT PHASE NOISE
VBAT = 3.8 V,
C_L3 = 10 pF,
R_L3 = 10 kW
SYSCLK_IN
500 mV/div
SIN_SYSCLK3
500 mV/div
10 ns/div
Figure 43.
CLOCK DISTRIBUTION/SIN_SYSCLK1
OUTPUT PHASE NOISE
VBAT = 3.8 V,
C_L1 = 15 pF,
R_L1 = 3 kW
Figure 44.
CLOCK DISTRIBUTION/SIN_SYSCLK2
OUTPUT PHASE NOISE
VBAT = 3.8 V,
C_L2 = 10 pF,
R_L2 = 10 kW
Figure 45.
Figure 46.
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