TMS470R1A384 Datasheet, PDF (36/63 Pages) Texas Instruments – 16/32-Bit RISC Flash Microcontroller

TMS470R1A384
16/32-Bit RISC Flash Microcontroller
SPNS110B – AUGUST 2005 – REVISED AUGUST 2006
ZPLL AND CLOCK SPECIFICATIONS
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Timing Requirements for ZPLL Circuits Enabled or Disabled
f_(OSC)
t_c(OSC)
t_w(OSCIL)
t_w(OSCIH)
f_(OSCRST)
Input clock frequency
Cycle time, OSCIN
Pulse duration, OSCIN low
Pulse duration, OSCIN high
OSC FAIL frequency⁽¹⁾
MIN
TYP MAX UNIT
4
20 MHz
50
ns
15
ns
15
ns
53
kHz
(1) Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL.15) and the OSC FAIL flag (GLBSTAT.1)
bits equal to 1. For more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).
Switching Characteristics Over Recommended Operating Conditions for Clocks⁽¹⁾⁽²⁾
PARAMETER
TEST CONDITIONS⁽³⁾
MIN
MAX UNIT
f_(SYS)
System clock frequency⁽⁴⁾
Pipeline mode enabled
Pipeline mode disabled
48 MHz
24 MHz
f_(CONFIG)
f_(ICLK)
f_(ECLK)
t_c(SYS)
System clock frequency - flash config mode
Interface clock frequency
External clock output frequency for ECP module
Cycle time, system clock
Pipeline mode enabled
Pipeline mode disabled
24 MHz
24 MHz
24 MHz
20.8
ns
41.6
ns
t_c(CONFIG)
t_c(ICLK)
t_c(ECLK)
Cycle time, system clock - flash config mode
Cycle time, interface clock
Cycle time, ECP module external clock output
41.6
ns
41.6
ns
41.6
ns
(1) f_(SYS) = M × f_(OSC) / R, where M = {8}, R = {1,2,3,4,5,6,7,8} when PLLDIS = 0. R is the system-clock divider determined by the
CLKDIVPRE [2:0] bits in the global control register (GLBCTRL[2:0]) and M is the PLL multiplier determined by the MULT4 bit also in the
GLBCTRL register (GLBCTRL.3).
f_(SYS) = f_(OSC) / R, where R = {1,2,3,4,5,6,7,8} when PLLDIS = 1.
f_(ICLK) = f_(SYS) / X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1]
bits in the SYS module.
(2) f_(ECLK) = f_(ICLK) / N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module.
(3) Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT.0).
(4) Flash Vread must be set to 5 V to achieve maximum system clock frequency.
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