TMS320C5X Datasheet, PDF (36/91 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
with its long-immediate operand. The long-immediate operand is the address of the instruction following the last
instruction in the loop minus one. (The repeat block must contain at least three instruction words.) Execution
of the RPTB instruction automatically sets active the BRAF bit. With each PC update, the PAER contents are
compared to the PC. If they are equal, the BRCR contents are compared to zero. If the BRCR contents are
greater than zero, BRCR is decremented and the PASR is loaded into the PC, repeating the loop. If not, the
BRAF bit is set low and the processor resumes execution past the end of the code’s loop.
The equivalent of a WHILE loop can be implemented by setting the BRAF bit to zero if the exit condition is met.
The program then completes the current pass through the loop but does not go back to the top. To exit, the bit
must be reset at least four instruction words before the end of the loop. It is possible to exit block-repeat loops
and return to them without stopping and restarting the loop. Branches, calls, and interrupts do not necessarily
affect the loop. When program control is returned to the loop, loop execution is resumed.
instruction set summary
This section summarizes the operational codes (opcodes) of the instruction set for the ’C5x digital signal
processors. The instruction set is a super set of the ’C1x and ’C2x instruction sets. The instructions are arranged
according to function and are alphabetized by mnemonic within each category. The symbols in Table 6 are used
in the instruction set opcode table (Table 7). T he Texas Instruments ’C5x assembler accepts ’C2x instructions
as well as ’C5x instructions.
The number of words that an instruction occupies in program memory is specified in column 4 of Table 7. In
these cases, different forms of the instruction occupy a different number of words. For example, the ADD
instruction occupies one word when the operand is a short immediate value or two words if the operand is a
long immediate value.
The number of cycles that an instruction requires to execute is listed in column 5 of Table 7. All instructions are
assumed to be executed from internal program memory and internal data dual-access memory. The cycle
timings are for single-instruction execution, not for repeat mode.
A read or write access to any peripheral memory-mapped register in data memory locations 20h – 4Fh adds one
cycle to the cycle time shown because all peripherals perform these accesses over the internal peripheral bus.
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