ADSP-21160NCB-100 Datasheet, PDF (35/60 Pages) Texas Instruments – Digital Signal Processor

ADSP-21160M/ADSP-21160N
Asynchronous Read/Write—Host to ADSP-21160x
Use these specifications (Table 23, Table 24, Figure 20, and
Figure 21) for asynchronous host processor accesses of an
ADSP-21160x, after the host has asserted CS and HBR (low).
Table 23. Read Cycle
Parameter
Timing Requirements
t_SADRDL
t_HADRDH
t_WRWH
t_DRDHRDY
t_DRDHRDY
Address Setup/CS Low Before RDx Low
Address Hold/CS Hold Low After RDx
RDx/WRx High Width
RDx High Delay After REDY (O/D) Disable
RDx High Delay After REDY (A/D) Disable
Switching Characteristics
t_SDATRDY
t_DRDYRDL
t_RDYPRD
t_HDARWH
Data Valid Before REDY Disable from Low
REDY (O/D) or (A/D) Low Delay After RDx Low¹
REDY (O/D) or (A/D) Low Pulsewidth for Read²
Data Disable After RDx High³
1 _{For ADSP-21160M, specification is 7 ns, minimum.}
2 _{For ADSP-21160M, specification is tCK ns, minimum.}
3 _{For ADSP-21160M, specification is 2 ns, minimum.}
Table 24. Write Cycle
Parameter
Timing Requirements
t_SCSWRL
t_HCSWRH
t_SADWRH
t_HADWRH
t_WWRL
t_WRWH
t_DWRHRDY
t_SDATWH
t_HDATWH
CS Low Setup Before WRx Low
CS Low Hold After WRx High
Address Setup Before WRx High
Address Hold After WRx High
WRx Low Width¹
RDx/WRx High Width
WRx High Delay After REDY (O/D) or (A/D) Disable
Data Setup Before WRx High
Data Hold After WRx High
Switching Characteristics
t_DRDYWRL
t_RDYPWR
REDY (O/D) or (A/D) Low Delay After WRx/CS Low
REDY (O/D) or (A/D) Low Pulsewidth for Write²
1 _{For ADSP-21160M, specification is 7 ns, minimum.}
2 _{For ADSP-21160M, specification is 12 ns, minimum.}
After HBG is returned by the ADSP-21160x, the host can drive
the RDx and WRx pins to access the ADSP-21160x DSP’s
internal memory or IOP registers. HBR and HBG are assumed
low for this timing.
Min
Max
Unit
0
ns
2
ns
5
ns
0
ns
0
ns
2
ns
11
ns
t_CK – 4
ns
1.5
6
ns
Min
0
0
6
2
t_CCLK+1
5
0
5
4
5.75 + 0.5t_CCLK
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
ns
ns
Rev. C | Page 35 of 60 | February 2013